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-rw-r--r--llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp22
-rw-r--r--llvm/lib/CodeGen/LiveDebugValues.cpp4
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp16
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfo.cpp31
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp16
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp20
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.h12
-rw-r--r--llvm/lib/Target/Lanai/LanaiInstrInfo.cpp7
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.cpp14
9 files changed, 85 insertions, 57 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 09a7de60724..c8e564ea939 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -750,18 +750,28 @@ static bool emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
const MachineFrameInfo &MFI = MF->getFrameInfo();
bool Commented = false;
+ auto getSize = [&MFI](
+ const SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) {
+ unsigned Size = 0;
+ for (auto &A : Accesses)
+ if (MFI.isSpillSlotObjectIndex(A.FI))
+ Size += A.MMO->getSize();
+ return Size;
+ };
+
// We assume a single instruction only has a spill or reload, not
// both.
const MachineMemOperand *MMO;
+ SmallVector<TargetInstrInfo::FrameAccess, 2> Accesses;
if (TII->isLoadFromStackSlotPostFE(MI, FI)) {
if (MFI.isSpillSlotObjectIndex(FI)) {
MMO = *MI.memoperands_begin();
CommentOS << MMO->getSize() << "-byte Reload";
Commented = true;
}
- } else if (TII->hasLoadFromStackSlot(MI, MMO, FI)) {
- if (MFI.isSpillSlotObjectIndex(FI)) {
- CommentOS << MMO->getSize() << "-byte Folded Reload";
+ } else if (TII->hasLoadFromStackSlot(MI, Accesses)) {
+ if (auto Size = getSize(Accesses)) {
+ CommentOS << Size << "-byte Folded Reload";
Commented = true;
}
} else if (TII->isStoreToStackSlotPostFE(MI, FI)) {
@@ -770,9 +780,9 @@ static bool emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
CommentOS << MMO->getSize() << "-byte Spill";
Commented = true;
}
- } else if (TII->hasStoreToStackSlot(MI, MMO, FI)) {
- if (MFI.isSpillSlotObjectIndex(FI)) {
- CommentOS << MMO->getSize() << "-byte Folded Spill";
+ } else if (TII->hasStoreToStackSlot(MI, Accesses)) {
+ if (auto Size = getSize(Accesses)) {
+ CommentOS << Size << "-byte Folded Spill";
Commented = true;
}
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp
index 417bd9d5aeb..dbc19b082d2 100644
--- a/llvm/lib/CodeGen/LiveDebugValues.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues.cpp
@@ -470,7 +470,7 @@ bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
MachineFunction *MF, unsigned &Reg) {
const MachineFrameInfo &FrameInfo = MF->getFrameInfo();
int FI;
- const MachineMemOperand *MMO;
+ SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
// TODO: Handle multiple stores folded into one.
if (!MI.hasOneMemOperand())
@@ -478,7 +478,7 @@ bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
// To identify a spill instruction, use the same criteria as in AsmPrinter.
if (!((TII->isStoreToStackSlotPostFE(MI, FI) ||
- TII->hasStoreToStackSlot(MI, MMO, FI)) &&
+ TII->hasStoreToStackSlot(MI, Accesses)) &&
FrameInfo.isSpillSlotObjectIndex(FI)))
return false;
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 3333e1f2fb8..d48f37f1ca6 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -3120,18 +3120,24 @@ void RAGreedy::reportNumberOfSplillsReloads(MachineLoop *L, unsigned &Reloads,
// Handle blocks that were not included in subloops.
if (Loops->getLoopFor(MBB) == L)
for (MachineInstr &MI : *MBB) {
- const MachineMemOperand *MMO;
+ SmallVector<TargetInstrInfo::FrameAccess, 2> Accesses;
if (TII->isLoadFromStackSlot(MI, FI) && MFI.isSpillSlotObjectIndex(FI))
++Reloads;
- else if (TII->hasLoadFromStackSlot(MI, MMO, FI) &&
- MFI.isSpillSlotObjectIndex(FI))
+ else if (TII->hasLoadFromStackSlot(MI, Accesses) &&
+ llvm::any_of(Accesses,
+ [&MFI](const TargetInstrInfo::FrameAccess &A) {
+ return MFI.isSpillSlotObjectIndex(A.FI);
+ }))
++FoldedReloads;
else if (TII->isStoreToStackSlot(MI, FI) &&
MFI.isSpillSlotObjectIndex(FI))
++Spills;
- else if (TII->hasStoreToStackSlot(MI, MMO, FI) &&
- MFI.isSpillSlotObjectIndex(FI))
+ else if (TII->hasStoreToStackSlot(MI, Accesses) &&
+ llvm::any_of(Accesses,
+ [&MFI](const TargetInstrInfo::FrameAccess &A) {
+ return MFI.isSpillSlotObjectIndex(A.FI);
+ }))
++FoldedSpills;
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 19670c24ae8..4d9aa830414 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -339,42 +339,37 @@ bool TargetInstrInfo::PredicateInstruction(
return MadeChange;
}
-bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const {
+bool TargetInstrInfo::hasLoadFromStackSlot(
+ const MachineInstr &MI, SmallVectorImpl<FrameAccess> &Accesses) const {
+
+ size_t StartSize = Accesses.size();
for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
oe = MI.memoperands_end();
o != oe; ++o) {
if ((*o)->isLoad()) {
if (const FixedStackPseudoSourceValue *Value =
dyn_cast_or_null<FixedStackPseudoSourceValue>(
- (*o)->getPseudoValue())) {
- FrameIndex = Value->getFrameIndex();
- MMO = *o;
- return true;
- }
+ (*o)->getPseudoValue()))
+ Accesses.emplace_back(*o, Value->getFrameIndex());
}
}
- return false;
+ return Accesses.size() != StartSize;
}
-bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const {
+bool TargetInstrInfo::hasStoreToStackSlot(
+ const MachineInstr &MI, SmallVectorImpl<FrameAccess> &Accesses) const {
+ size_t StartSize = Accesses.size();
for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
oe = MI.memoperands_end();
o != oe; ++o) {
if ((*o)->isStore()) {
if (const FixedStackPseudoSourceValue *Value =
dyn_cast_or_null<FixedStackPseudoSourceValue>(
- (*o)->getPseudoValue())) {
- FrameIndex = Value->getFrameIndex();
- MMO = *o;
- return true;
- }
+ (*o)->getPseudoValue()))
+ Accesses.emplace_back(*o, Value->getFrameIndex());
}
}
- return false;
+ return Accesses.size() != StartSize;
}
bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9a4614c1686..db7e751e060 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1172,8 +1172,12 @@ unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
- const MachineMemOperand *Dummy;
- return MI.mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
+ SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+ if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses)) {
+ FrameIndex = Accesses.begin()->FI;
+ return true;
+ }
+ return false;
}
void ARMBaseInstrInfo::
@@ -1386,8 +1390,12 @@ unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
- const MachineMemOperand *Dummy;
- return MI.mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
+ SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+ if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses)) {
+ FrameIndex = Accesses.begin()->FI;
+ return true;
+ }
+ return false;
}
/// Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 77eb28329f3..20ed6a995f2 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -335,37 +335,37 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
/// This function checks if the instruction or bundle of instructions
/// has load from stack slot and returns frameindex and machine memory
/// operand of that instruction if true.
-bool HexagonInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const {
+bool HexagonInstrInfo::hasLoadFromStackSlot(
+ const MachineInstr &MI,
+ SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
if (MI.isBundle()) {
const MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
- if (TargetInstrInfo::hasLoadFromStackSlot(*MII, MMO, FrameIndex))
+ if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
return true;
return false;
}
- return TargetInstrInfo::hasLoadFromStackSlot(MI, MMO, FrameIndex);
+ return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
}
/// This function checks if the instruction or bundle of instructions
/// has store to stack slot and returns frameindex and machine memory
/// operand of that instruction if true.
-bool HexagonInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const {
+bool HexagonInstrInfo::hasStoreToStackSlot(
+ const MachineInstr &MI,
+ SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
if (MI.isBundle()) {
const MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
- if (TargetInstrInfo::hasStoreToStackSlot(*MII, MMO, FrameIndex))
+ if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
return true;
return false;
}
- return TargetInstrInfo::hasStoreToStackSlot(MI, MMO, FrameIndex);
+ return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
}
/// This function can analyze one/two way branching only and should (mostly) be
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 817b27ede8f..d2125fc6852 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -69,16 +69,16 @@ public:
/// Check if the instruction or the bundle of instructions has
/// load from stack slots. Return the frameindex and machine memory operand
/// if true.
- bool hasLoadFromStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const override;
+ bool hasLoadFromStackSlot(
+ const MachineInstr &MI,
+ SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const override;
/// Check if the instruction or the bundle of instructions has
/// store to stack slots. Return the frameindex and machine memory operand
/// if true.
- bool hasStoreToStackSlot(const MachineInstr &MI,
- const MachineMemOperand *&MMO,
- int &FrameIndex) const override;
+ bool hasStoreToStackSlot(
+ const MachineInstr &MI,
+ SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const override;
/// Analyze the branching code at the end of MBB, returning
/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index 493d02bef37..398c84a2a19 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -733,8 +733,11 @@ unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
return Reg;
// Check for post-frame index elimination operations
- const MachineMemOperand *Dummy;
- return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
+ SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+ if (hasLoadFromStackSlot(MI, Accesses)){
+ FrameIndex = Accesses.begin()->FI;
+ return 1;
+ }
}
return 0;
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index f6d8e2cbc4c..06a4d1f86ce 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -411,8 +411,11 @@ unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
return Reg;
// Check for post-frame index elimination operations
- const MachineMemOperand *Dummy;
- return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
+ SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+ if (hasLoadFromStackSlot(MI, Accesses)) {
+ FrameIndex = Accesses.begin()->FI;
+ return 1;
+ }
}
return 0;
}
@@ -441,8 +444,11 @@ unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
return Reg;
// Check for post-frame index elimination operations
- const MachineMemOperand *Dummy;
- return hasStoreToStackSlot(MI, Dummy, FrameIndex);
+ SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+ if (hasStoreToStackSlot(MI, Accesses)) {
+ FrameIndex = Accesses.begin()->FI;
+ return 1;
+ }
}
return 0;
}
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