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-rw-r--r--llvm/lib/DebugInfo/CodeView/DebugFrameDataSubsection.cpp7
-rw-r--r--llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp14
-rw-r--r--llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp2
-rw-r--r--llvm/lib/Target/XCore/XCoreFrameLowering.cpp1
4 files changed, 10 insertions, 14 deletions
diff --git a/llvm/lib/DebugInfo/CodeView/DebugFrameDataSubsection.cpp b/llvm/lib/DebugInfo/CodeView/DebugFrameDataSubsection.cpp
index be8c32d5b29..9bc69abea10 100644
--- a/llvm/lib/DebugInfo/CodeView/DebugFrameDataSubsection.cpp
+++ b/llvm/lib/DebugInfo/CodeView/DebugFrameDataSubsection.cpp
@@ -47,10 +47,9 @@ Error DebugFrameDataSubsection::commit(BinaryStreamWriter &Writer) const {
}
std::vector<FrameData> SortedFrames(Frames.begin(), Frames.end());
- std::sort(SortedFrames.begin(), SortedFrames.end(),
- [](const FrameData &LHS, const FrameData &RHS) {
- return LHS.RvaStart < RHS.RvaStart;
- });
+ llvm::sort(SortedFrames, [](const FrameData &LHS, const FrameData &RHS) {
+ return LHS.RvaStart < RHS.RvaStart;
+ });
if (auto EC = Writer.writeArray(makeArrayRef(SortedFrames)))
return EC;
return Error::success();
diff --git a/llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp b/llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
index 96e074da122..c20b4714e2b 100644
--- a/llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
@@ -158,10 +158,8 @@ void JITLinkerBase::layOutAtoms() {
};
for (auto &KV : Layout) {
auto &SL = KV.second;
- std::sort(SL.ContentSections.begin(), SL.ContentSections.end(),
- CompareByOrdinal);
- std::sort(SL.ZeroFillSections.begin(), SL.ZeroFillSections.end(),
- CompareByOrdinal);
+ llvm::sort(SL.ContentSections, CompareByOrdinal);
+ llvm::sort(SL.ZeroFillSections, CompareByOrdinal);
}
}
@@ -188,10 +186,10 @@ void JITLinkerBase::layOutAtoms() {
OrderedLayoutHeads.push_back(DA);
// Now sort the list of layout heads by address.
- std::sort(OrderedLayoutHeads.begin(), OrderedLayoutHeads.end(),
- [](const DefinedAtom *LHS, const DefinedAtom *RHS) {
- return LHS->getAddress() < RHS->getAddress();
- });
+ llvm::sort(OrderedLayoutHeads,
+ [](const DefinedAtom *LHS, const DefinedAtom *RHS) {
+ return LHS->getAddress() < RHS->getAddress();
+ });
// Now populate the SI.Atoms field by appending each of the chains.
for (auto *DA : OrderedLayoutHeads) {
diff --git a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
index fcbc3cddf6e..fc95166354c 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
@@ -649,7 +649,7 @@ unsigned GCNRegBankReassign::tryReassign(Candidate &C) {
}
}
}
- std::sort(BankStalls.begin(), BankStalls.end());
+ llvm::sort(BankStalls);
unsigned OrigReg = VRM->getPhys(C.Reg);
LRM->unassign(LI);
diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
index 5066407c74a..8b313150609 100644
--- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
@@ -27,7 +27,6 @@
#include "llvm/IR/Function.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetOptions.h"
-#include <algorithm> // std::sort
using namespace llvm;
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