diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 13b92fc07a1..e41cf6e771b 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -4726,9 +4726,11 @@ SDValue SITargetLowering::lowerImage(SDValue Op, // Check for 16 bit addresses and pack if true. unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs; MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType(); - if (VAddrVT.getScalarType() == MVT::f16 && + const MVT VAddrScalarVT = VAddrVT.getScalarType(); + if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) && ST->hasFeature(AMDGPU::FeatureR128A16)) { IsA16 = true; + const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16; for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) { SDValue AddrLo, AddrHi; // Push back extra arguments. @@ -4747,7 +4749,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op, AddrHi = Op.getOperand(i + 1); i++; } - AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f16, + AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT, {AddrLo, AddrHi}); AddrLo = DAG.getBitcast(MVT::i32, AddrLo); } |
