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-rw-r--r--llvm/lib/Target/Hexagon/Hexagon.td19
-rw-r--r--llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp1
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp8
-rw-r--r--llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp5
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSubtarget.h5
-rw-r--r--llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp7
6 files changed, 34 insertions, 11 deletions
diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td
index cacf9fb9d13..92a7e554e36 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.td
+++ b/llvm/lib/Target/Hexagon/Hexagon.td
@@ -49,10 +49,14 @@ def ExtensionHVXDbl
: SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
"Hexagon HVX 128B instructions", [ExtensionHVX128B]>;
+def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
+ "Support for instruction packets">;
def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
"Use constant-extended calls">;
def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
"Supports mem_noshuf feature">;
+def FeatureNVJ : SubtargetFeature<"nvj", "UseNewValueJumps", "true",
+ "Support for new-value jumps", [FeaturePackets]>;
def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true",
"Enable generation of duplex instruction">;
def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
@@ -323,18 +327,21 @@ class Proc<string Name, SchedMachineModel Model,
: ProcessorModel<Name, Model, Features>;
def : Proc<"hexagonv4", HexagonModelV4,
- [ArchV4, FeatureDuplex]>;
+ [ArchV4, FeaturePackets, FeatureNVJ, FeatureDuplex]>;
def : Proc<"hexagonv5", HexagonModelV4,
- [ArchV4, ArchV5, FeatureDuplex]>;
+ [ArchV4, ArchV5, FeaturePackets, FeatureNVJ, FeatureDuplex]>;
def : Proc<"hexagonv55", HexagonModelV55,
- [ArchV4, ArchV5, ArchV55, FeatureDuplex]>;
+ [ArchV4, ArchV5, ArchV55, FeaturePackets, FeatureNVJ,
+ FeatureDuplex]>;
def : Proc<"hexagonv60", HexagonModelV60,
- [ArchV4, ArchV5, ArchV55, ArchV60, FeatureDuplex]>;
+ [ArchV4, ArchV5, ArchV55, ArchV60, FeaturePackets, FeatureNVJ,
+ FeatureDuplex]>;
def : Proc<"hexagonv62", HexagonModelV62,
- [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeatureDuplex]>;
+ [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeaturePackets,
+ FeatureNVJ, FeatureDuplex]>;
def : Proc<"hexagonv65", HexagonModelV65,
[ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
- FeatureMemNoShuf, FeatureDuplex]>;
+ FeatureMemNoShuf, FeaturePackets, FeatureNVJ, FeatureDuplex]>;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index 68b1fe6bf4b..3a1821bf265 100644
--- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -748,6 +748,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
if (MI->isBundle()) {
+ assert(Subtarget->usePackets() && "Support for packets is disabled");
const MachineBasicBlock* MBB = MI->getParent();
MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
index 46f5bb4de8a..97d5565d059 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
@@ -2035,6 +2035,10 @@ void HexagonDAGToDAGISel::SelectHvxVAlign(SDNode *N) {
}
void HexagonDAGToDAGISel::SelectV65GatherPred(SDNode *N) {
+ if (!HST->usePackets()) {
+ report_fatal_error("Support for gather requires packets, "
+ "which are disabled");
+ }
const SDLoc &dl(N);
SDValue Chain = N->getOperand(0);
SDValue Address = N->getOperand(2);
@@ -2075,6 +2079,10 @@ void HexagonDAGToDAGISel::SelectV65GatherPred(SDNode *N) {
}
void HexagonDAGToDAGISel::SelectV65Gather(SDNode *N) {
+ if (!HST->usePackets()) {
+ report_fatal_error("Support for gather requires packets, "
+ "which are disabled");
+ }
const SDLoc &dl(N);
SDValue Chain = N->getOperand(0);
SDValue Address = N->getOperand(2);
diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
index bb733fed044..2608096b87d 100644
--- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -24,6 +24,7 @@
#include "Hexagon.h"
#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
@@ -461,9 +462,9 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
MF.getSubtarget().getRegisterInfo());
MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
- if (DisableNewValueJumps) {
+ if (DisableNewValueJumps ||
+ !MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
return false;
- }
int nvjCount = DbgNVJCount;
int nvjGenerated = 0;
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
index 87121b30906..9076b1d7fd6 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -48,6 +48,8 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
bool UseMemOps, UseHVX64BOps, UseHVX128BOps;
bool UseLongCalls;
+ bool UsePackets = false;
+ bool UseNewValueJumps = false;
bool ModeIEEERndNear;
bool HasMemNoShuf = false;
@@ -153,6 +155,9 @@ public:
bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
+ bool usePackets() const { return UsePackets; }
+ bool useNewValueJumps() const { return UseNewValueJumps; }
+
bool hasMemNoShuf() const { return HasMemNoShuf; }
bool hasReservedR19() const { return ReservedR19; }
bool useLongCalls() const { return UseLongCalls; }
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index c2404235091..16d3733b92e 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -199,11 +199,12 @@ static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI,
}
bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
- if (DisablePacketizer || skipFunction(MF.getFunction()))
+ auto &HST = MF.getSubtarget<HexagonSubtarget>();
+ if (DisablePacketizer || !HST.usePackets() || skipFunction(MF.getFunction()))
return false;
- HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
- HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
+ HII = HST.getInstrInfo();
+ HRI = HST.getRegisterInfo();
auto &MLI = getAnalysis<MachineLoopInfo>();
auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
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