diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.h | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonPatterns.td | 13 |
4 files changed, 5 insertions, 28 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 7b5273b561e..c079d737d38 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -983,15 +983,11 @@ void HvxSelector::materialize(const ResultStack &Results) { MVT OpTy = Op.getValueType().getSimpleVT(); if (Part != OpRef::Whole) { assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); - if (Op.getOpcode() == HexagonISD::VCOMBINE) { - Op = (Part == OpRef::HiHalf) ? Op.getOperand(0) : Op.getOperand(1); - } else { - MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), - OpTy.getVectorNumElements()/2); - unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo - : Hexagon::vsub_hi; - Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); - } + MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), + OpTy.getVectorNumElements()/2); + unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo + : Hexagon::vsub_hi; + Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); } Ops.push_back(Op); } // for (Node : Results) diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index caa45d0fb0c..3c5793ce9f7 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2281,9 +2281,6 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::JT: return "HexagonISD::JT"; case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN"; - case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE"; - case HexagonISD::VPACKE: return "HexagonISD::VPACKE"; - case HexagonISD::VPACKO: return "HexagonISD::VPACKO"; case HexagonISD::VASL: return "HexagonISD::VASL"; case HexagonISD::VASR: return "HexagonISD::VASR"; case HexagonISD::VLSR: return "HexagonISD::VLSR"; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index bfad5037dac..0bc230728d8 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -59,9 +59,6 @@ namespace HexagonISD { TSTBIT, INSERT, EXTRACTU, - VCOMBINE, - VPACKE, - VPACKO, VEXTRACTW, VINSERTW0, VROR, diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index f39dc7bbf57..a6ac61cf796 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -970,14 +970,8 @@ def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), def SDTHexagonI64I32I32: SDTypeProfile<1, 2, [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; -def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, - SDTCisSubVecOfVec<1, 0>]>; -def SDTHexagonVPACK: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisVec<1>]>; def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; -def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>; -def HexagonVPACKE: SDNode<"HexagonISD::VPACKE", SDTHexagonVPACK>; -def HexagonVPACKO: SDNode<"HexagonISD::VPACKO", SDTHexagonVPACK>; def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; @@ -2999,13 +2993,6 @@ def Combinev: OutPatFrag<(ops node:$Rs, node:$Rt), def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>; def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>; -let Predicates = [UseHVX] in { - def: OpR_RR_pat<V6_vpackeb, pf2<HexagonVPACKE>, VecI8, HVI8>; - def: OpR_RR_pat<V6_vpackob, pf2<HexagonVPACKO>, VecI8, HVI8>; - def: OpR_RR_pat<V6_vpackeh, pf2<HexagonVPACKE>, VecI16, HVI16>; - def: OpR_RR_pat<V6_vpackoh, pf2<HexagonVPACKO>, VecI16, HVI16>; -} - def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>; def vzero: PatFrag<(ops), (HexagonVZERO)>; |
