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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 37beff96191..c9fc812259a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -597,10 +597,11 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
// Grab the destination register
const TargetRegisterClass *DRC = 0;
DRC = RegInfo.getRegClass(VRBase);
- assert(SRC == DRC &&
+ assert(SRC && DRC && SRC == DRC &&
"Source subregister and destination must have the same class");
} else {
// Create the reg
+ assert(SRC && "Couldn't find source register class");
VRBase = RegInfo.createVirtualRegister(SRC);
}
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