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-rw-r--r--llvm/lib/CodeGen/RegisterPressure.cpp35
-rw-r--r--llvm/lib/Support/SourceMgr.cpp4
-rw-r--r--llvm/lib/Support/TargetRegistry.cpp5
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelLowering.cpp3
-rw-r--r--llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp8
-rw-r--r--llvm/lib/Target/ARM/ARMConstantIslandPass.cpp5
-rw-r--r--llvm/lib/Target/ARM/ARMFrameLowering.cpp3
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp2
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp10
10 files changed, 34 insertions, 45 deletions
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index a21d6c1d4d6..dba8929ef05 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -328,10 +328,9 @@ void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) {
static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
unsigned RegUnit) {
- auto I = std::find_if(RegUnits.begin(), RegUnits.end(),
- [RegUnit](const RegisterMaskPair Other) {
- return Other.RegUnit == RegUnit;
- });
+ auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ return Other.RegUnit == RegUnit;
+ });
if (I == RegUnits.end())
return 0;
return I->LaneMask;
@@ -341,10 +340,9 @@ static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
RegisterMaskPair Pair) {
unsigned RegUnit = Pair.RegUnit;
assert(Pair.LaneMask != 0);
- auto I = std::find_if(RegUnits.begin(), RegUnits.end(),
- [RegUnit](const RegisterMaskPair Other) {
- return Other.RegUnit == RegUnit;
- });
+ auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ return Other.RegUnit == RegUnit;
+ });
if (I == RegUnits.end()) {
RegUnits.push_back(Pair);
} else {
@@ -354,10 +352,9 @@ static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
static void setRegZero(SmallVectorImpl<RegisterMaskPair> &RegUnits,
unsigned RegUnit) {
- auto I = std::find_if(RegUnits.begin(), RegUnits.end(),
- [RegUnit](const RegisterMaskPair Other) {
- return Other.RegUnit == RegUnit;
- });
+ auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ return Other.RegUnit == RegUnit;
+ });
if (I == RegUnits.end()) {
RegUnits.push_back(RegisterMaskPair(RegUnit, 0));
} else {
@@ -369,10 +366,9 @@ static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
RegisterMaskPair Pair) {
unsigned RegUnit = Pair.RegUnit;
assert(Pair.LaneMask != 0);
- auto I = std::find_if(RegUnits.begin(), RegUnits.end(),
- [RegUnit](const RegisterMaskPair Other) {
- return Other.RegUnit == RegUnit;
- });
+ auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ return Other.RegUnit == RegUnit;
+ });
if (I != RegUnits.end()) {
I->LaneMask &= ~Pair.LaneMask;
if (I->LaneMask == 0)
@@ -676,10 +672,9 @@ void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
assert(Pair.LaneMask != 0);
unsigned RegUnit = Pair.RegUnit;
- auto I = std::find_if(LiveInOrOut.begin(), LiveInOrOut.end(),
- [RegUnit](const RegisterMaskPair &Other) {
- return Other.RegUnit == RegUnit;
- });
+ auto I = find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
+ return Other.RegUnit == RegUnit;
+ });
LaneBitmask PrevMask;
LaneBitmask NewMask;
if (I == LiveInOrOut.end()) {
diff --git a/llvm/lib/Support/SourceMgr.cpp b/llvm/lib/Support/SourceMgr.cpp
index 6d44a4d51f6..395c29b4279 100644
--- a/llvm/lib/Support/SourceMgr.cpp
+++ b/llvm/lib/Support/SourceMgr.cpp
@@ -14,6 +14,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/Support/SourceMgr.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Locale.h"
#include "llvm/Support/MemoryBuffer.h"
@@ -395,8 +396,7 @@ void SMDiagnostic::print(const char *ProgName, raw_ostream &S, bool ShowColors,
// map like Clang's TextDiagnostic. For now, we'll just handle tabs by
// expanding them later, and bail out rather than show incorrect ranges and
// misaligned fixits for any other odd characters.
- if (std::find_if(LineContents.begin(), LineContents.end(), isNonASCII) !=
- LineContents.end()) {
+ if (find_if(LineContents, isNonASCII) != LineContents.end()) {
printSourceLine(S, LineContents);
return;
}
diff --git a/llvm/lib/Support/TargetRegistry.cpp b/llvm/lib/Support/TargetRegistry.cpp
index 02a6d334b91..bed9ed64f80 100644
--- a/llvm/lib/Support/TargetRegistry.cpp
+++ b/llvm/lib/Support/TargetRegistry.cpp
@@ -30,8 +30,7 @@ const Target *TargetRegistry::lookupTarget(const std::string &ArchName,
// name, because it might be a backend that has no mapping to a target triple.
const Target *TheTarget = nullptr;
if (!ArchName.empty()) {
- auto I =
- std::find_if(targets().begin(), targets().end(),
+ auto I = find_if(targets(),
[&](const Target &T) { return ArchName == T.getName(); });
if (I == targets().end()) {
@@ -70,7 +69,7 @@ const Target *TargetRegistry::lookupTarget(const std::string &TT,
}
Triple::ArchType Arch = Triple(TT).getArch();
auto ArchMatch = [&](const Target &T) { return T.ArchMatchFn(Arch); };
- auto I = std::find_if(targets().begin(), targets().end(), ArchMatch);
+ auto I = find_if(targets(), ArchMatch);
if (I == targets().end()) {
Error = "No available targets are compatible with this triple.";
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a11b032e3f8..66f37c88ae5 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5162,8 +5162,7 @@ static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
unsigned &Imm) {
// Look for the first non-undef element.
- const int *FirstRealElt = std::find_if(M.begin(), M.end(),
- [](int Elt) {return Elt >= 0;});
+ const int *FirstRealElt = find_if(M, [](int Elt) { return Elt >= 0; });
// Benefit form APInt to handle overflow when calculating expected element.
unsigned NumElts = VT.getVectorNumElements();
diff --git a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
index 4e106bd732c..53f30f88d10 100644
--- a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
@@ -354,10 +354,10 @@ private:
if (Src.first->getReg() != AMDGPU::ALU_LITERAL_X)
continue;
int64_t Imm = Src.second;
- std::vector<MachineOperand*>::iterator It =
- std::find_if(Lits.begin(), Lits.end(),
- [&](MachineOperand* val)
- { return val->isImm() && (val->getImm() == Imm);});
+ std::vector<MachineOperand *>::iterator It =
+ find_if(Lits, [&](MachineOperand *val) {
+ return val->isImm() && (val->getImm() == Imm);
+ });
// Get corresponding Operand
MachineOperand &Operand = MI.getOperand(
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index e4fefef2683..aac6c5bcf5d 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -2056,9 +2056,8 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
// record the TBB or TBH use.
int CPEntryIdx = JumpTableEntryIndices[JTI];
auto &CPEs = CPEntries[CPEntryIdx];
- auto Entry = std::find_if(CPEs.begin(), CPEs.end(), [&](CPEntry &E) {
- return E.CPEMI == User.CPEMI;
- });
+ auto Entry =
+ find_if(CPEs, [&](CPEntry &E) { return E.CPEMI == User.CPEMI; });
++Entry->RefCount;
CPUsers.emplace_back(CPUser(NewJTMI, User.CPEMI, 4, false, false));
}
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 9e79faa3abf..853507527e0 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -196,8 +196,7 @@ struct StackAdjustingInsts {
}
void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
- auto Info = std::find_if(Insts.begin(), Insts.end(),
- [&](InstInfo &Info) { return Info.I == I; });
+ auto Info = find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
assert(Info != Insts.end() && "invalid sp adjusting instruction");
Info->SPAdjust += ExtraBytes;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index d4b54e3ddd0..76dcc617697 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -2731,7 +2731,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
auto LoopInpEq = [G] (const PhiInfo &P) -> bool {
return G.Out.Reg == P.LR.Reg;
};
- if (std::find_if(Phis.begin(), Phis.end(), LoopInpEq) == Phis.end())
+ if (find_if(Phis, LoopInpEq) == Phis.end())
continue;
G.Inp.Reg = Inputs.find_first();
@@ -2756,7 +2756,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
auto LoopInpEq = [G] (const PhiInfo &P) -> bool {
return G.Out.Reg == P.LR.Reg;
};
- auto F = std::find_if(Phis.begin(), Phis.end(), LoopInpEq);
+ auto F = find_if(Phis, LoopInpEq);
if (F == Phis.end())
continue;
unsigned PrehR = 0;
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 2530b5f158e..17f227adda8 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -838,7 +838,7 @@ void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
return C.getReg() == Reg;
};
- auto F = std::find_if(CSI.begin(), CSI.end(), IfR);
+ auto F = find_if(CSI, IfR);
if (F == CSI.end())
continue;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8903c861276..af97864043a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8406,9 +8406,9 @@ static SDValue lowerVectorShuffleAsElementInsertion(
MVT ExtVT = VT;
MVT EltVT = VT.getVectorElementType();
- int V2Index = std::find_if(Mask.begin(), Mask.end(),
- [&Mask](int M) { return M >= (int)Mask.size(); }) -
- Mask.begin();
+ int V2Index =
+ find_if(Mask, [&Mask](int M) { return M >= (int)Mask.size(); }) -
+ Mask.begin();
bool IsV1Zeroable = true;
for (int i = 0, Size = Mask.size(); i < Size; ++i)
if (i != V2Index && !Zeroable[i]) {
@@ -9141,9 +9141,7 @@ static SDValue lowerVectorShuffleWithSHUFPS(const SDLoc &DL, MVT VT,
int NumV2Elements = count_if(Mask, [](int M) { return M >= 4; });
if (NumV2Elements == 1) {
- int V2Index =
- std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
- Mask.begin();
+ int V2Index = find_if(Mask, [](int M) { return M >= 4; }) - Mask.begin();
// Compute the index adjacent to V2Index and in the same half by toggling
// the low bit.
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