diff options
Diffstat (limited to 'llvm/lib')
42 files changed, 235 insertions, 197 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp index c6166e2365a..dc843856cd6 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp @@ -111,7 +111,12 @@ void AsmPrinter::EmitInlineAsm(StringRef Str, const MDNode *LocMDNode) const { OwningPtr<MCAsmParser> Parser(createMCAsmParser(TM.getTarget(), SrcMgr, OutContext, OutStreamer, *MAI)); - OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*Parser, TM)); + + OwningPtr<TargetAsmParser> + TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(), + TM.getTargetCPU(), + TM.getTargetFeatureString(), + *Parser)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index 318bf976d40..e3337e4c12d 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -98,10 +98,10 @@ static cl::opt<cl::boolOrDefault> EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector")); -LLVMTargetMachine::LLVMTargetMachine(const Target &T, - const std::string &Triple) - : TargetMachine(T), TargetTriple(Triple) { - AsmInfo = T.createAsmInfo(TargetTriple); +LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, + StringRef CPU, StringRef FS) + : TargetMachine(T, Triple, CPU, FS) { + AsmInfo = T.createAsmInfo(Triple); } // Set the default code model for the JIT for a generic target. @@ -143,7 +143,7 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, TargetAsmBackend *TAB = 0; if (ShowMCEncoding) { MCE = getTarget().createCodeEmitter(*this, *Context); - TAB = getTarget().createAsmBackend(TargetTriple); + TAB = getTarget().createAsmBackend(getTargetTriple()); } MCStreamer *S = getTarget().createAsmStreamer(*Context, Out, @@ -160,12 +160,12 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, // Create the code emitter for the target if it exists. If not, .o file // emission fails. MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context); - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); if (MCE == 0 || TAB == 0) return true; - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context, - *TAB, Out, MCE, + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), + *Context, *TAB, Out, MCE, hasMCRelaxAll(), hasMCNoExecStack())); AsmStreamer.get()->InitSections(); @@ -241,12 +241,12 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, // Create the code emitter for the target if it exists. If not, .o file // emission fails. MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx); - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple); + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple()); if (MCE == 0 || TAB == 0) return true; OwningPtr<MCStreamer> AsmStreamer; - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx, + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx, *TAB, Out, MCE, hasMCRelaxAll(), hasMCNoExecStack())); diff --git a/llvm/lib/MC/MCDisassembler/EDDisassembler.cpp b/llvm/lib/MC/MCDisassembler/EDDisassembler.cpp index 7f9fcc3af5e..a39f002a322 100644 --- a/llvm/lib/MC/MCDisassembler/EDDisassembler.cpp +++ b/llvm/lib/MC/MCDisassembler/EDDisassembler.cpp @@ -171,7 +171,7 @@ EDDisassembler::EDDisassembler(CPUKey &key) : std::string featureString; TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU, featureString)); - + const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo(); if (!registerInfo) @@ -183,7 +183,7 @@ EDDisassembler::EDDisassembler(CPUKey &key) : if (!AsmInfo) return; - + Disassembler.reset(Tgt->createMCDisassembler()); if (!Disassembler) @@ -371,8 +371,10 @@ int EDDisassembler::parseInst(SmallVectorImpl<MCParsedAsmOperand*> &operands, OwningPtr<MCAsmParser> genericParser(createMCAsmParser(*Tgt, sourceMgr, context, *streamer, *AsmInfo)); - OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*genericParser, - *TargetMachine)); + + StringRef triple = tripleFromArch(Key.Arch); + OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "", + *genericParser)); AsmToken OpcodeToken = genericParser->Lex(); AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to diff --git a/llvm/lib/MC/MCDisassembler/EDDisassembler.h b/llvm/lib/MC/MCDisassembler/EDDisassembler.h index 2fcc09d4bef..11d69c151cf 100644 --- a/llvm/lib/MC/MCDisassembler/EDDisassembler.h +++ b/llvm/lib/MC/MCDisassembler/EDDisassembler.h @@ -41,6 +41,7 @@ class MCInstPrinter; class MCInst; class MCParsedAsmOperand; class MCStreamer; +class MCSubtargetInfo; template <typename T> class SmallVectorImpl; class SourceMgr; class Target; diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index a5bd79db9f4..788b9450b21 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -147,35 +147,48 @@ def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // -def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate; +def HasV4T : Predicate<"Subtarget->hasV4TOps()">, + AssemblerPredicate<"HasV4TOps">; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">; -def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate; -def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate; +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, + AssemblerPredicate<"HasV5TEOps">; +def HasV6 : Predicate<"Subtarget->hasV6Ops()">, + AssemblerPredicate<"HasV6Ops">; def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; -def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate; +def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, + AssemblerPredicate<"HasV6T2Ops">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; -def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate; +def HasV7 : Predicate<"Subtarget->hasV7Ops()">, + AssemblerPredicate<"HasV7Ops">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">; -def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate; -def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate; -def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate; -def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate; -def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate; +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, + AssemblerPredicate<"FeatureVFP2">; +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, + AssemblerPredicate<"FeatureVFP3">; +def HasNEON : Predicate<"Subtarget->hasNEON()">, + AssemblerPredicate<"FeatureNEON">; +def HasFP16 : Predicate<"Subtarget->hasFP16()">, + AssemblerPredicate<"FeatureFP16">; +def HasDivide : Predicate<"Subtarget->hasDivide()">, + AssemblerPredicate<"FeatureHWDiv">; def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureT2XtPk">; def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureDSPThumb2">; def HasDB : Predicate<"Subtarget->hasDataBarrier()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureDB">; def HasMP : Predicate<"Subtarget->hasMPExtension()">, - AssemblerPredicate; + AssemblerPredicate<"FeatureMP">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; -def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate; +def IsThumb : Predicate<"Subtarget->isThumb()">, + AssemblerPredicate<"ModeThumb">; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; -def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate; -def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate; +def IsThumb2 : Predicate<"Subtarget->isThumb2()">, + AssemblerPredicate<"ModeThumb,FeatureThumb2">; +def IsARM : Predicate<"!Subtarget->isThumb()">, + AssemblerPredicate<"!ModeThumb">; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 506fe803621..f4fca351d44 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -18,9 +18,10 @@ #include "llvm/Support/CommandLine.h" #include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "ARMGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index bb3184ee73b..fd7b3bf538f 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -80,7 +80,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 6952c384f44..5cf3633b430 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -20,6 +20,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Support/SourceMgr.h" @@ -28,6 +29,10 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" + +#define GET_SUBTARGETINFO_ENUM +#include "ARMGenSubtargetInfo.inc" + using namespace llvm; namespace { @@ -36,7 +41,7 @@ class ARMOperand; class ARMAsmParser : public TargetAsmParser { MCAsmParser &Parser; - TargetMachine &TM; + MCSubtargetInfo *STI; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -79,6 +84,15 @@ class ARMAsmParser : public TargetAsmParser { void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode); + bool isThumb() const { + // FIXME: Can tablegen auto-generate this? + return (STI->getFeatureBits() & ARM::ModeThumb) != 0; + } + + bool isThumbOne() const { + return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0; + } + /// @name Auto-generated Match Functions /// { @@ -113,13 +127,15 @@ class ARMAsmParser : public TargetAsmParser { const SmallVectorImpl<MCParsedAsmOperand*> &); public: - ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) - : TargetAsmParser(T), Parser(_Parser), TM(_TM) { - MCAsmParserExtension::Initialize(_Parser); - // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures( - &TM.getSubtarget<ARMSubtarget>())); - } + ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + MCAsmParser &_Parser) + : TargetAsmParser(T), Parser(_Parser) { + STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); + + MCAsmParserExtension::Initialize(_Parser); + // Initialize the set of available features. + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + } virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands); @@ -1852,9 +1868,6 @@ static StringRef SplitMnemonic(StringRef Mnemonic, void ARMAsmParser:: GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { - bool isThumbOne = TM.getSubtarget<ARMSubtarget>().isThumb1Only(); - bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb(); - if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || @@ -1863,7 +1876,7 @@ GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || Mnemonic == "eor" || Mnemonic == "smlal" || - (Mnemonic == "mov" && !isThumbOne)) { + (Mnemonic == "mov" && !isThumbOne())) { CanAcceptCarrySet = true; } else { CanAcceptCarrySet = false; @@ -1880,7 +1893,7 @@ GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, CanAcceptPredicationCode = true; } - if (isThumb) + if (isThumb()) if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") CanAcceptPredicationCode = false; @@ -2207,12 +2220,12 @@ bool ARMAsmParser::ParseDirectiveCode(SMLoc L) { // includes Feature_IsThumb or not to match the right instructions. This is // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. if (Val == 16){ - assert(TM.getSubtarget<ARMSubtarget>().isThumb() && + assert(isThumb() && "switching between arm/thumb not yet suppported via .code 16)"); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); } else{ - assert(!TM.getSubtarget<ARMSubtarget>().isThumb() && + assert(!isThumb() && "switching between thumb/arm not yet suppported via .code 32)"); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 1db33b5e92d..0a8e3b171d8 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -23,65 +23,12 @@ #define GET_INSTRINFO_MC_DESC #include "ARMGenInstrInfo.inc" +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #include "ARMGenSubtargetInfo.inc" using namespace llvm; -MCInstrInfo *createARMMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitARMMCInstrInfo(X); - return X; -} - -MCRegisterInfo *createARMMCRegisterInfo() { - MCRegisterInfo *X = new MCRegisterInfo(); - InitARMMCRegisterInfo(X); - return X; -} - -MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - std::string ArchFS = ARM_MC::ParseARMTriple(TT); - if (!FS.empty()) { - if (!ArchFS.empty()) - ArchFS = ArchFS + "," + FS.str(); - else - ArchFS = FS; - } - - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitARMMCSubtargetInfo(X, CPU, ArchFS); - return X; -} - -// Force static initialization. -extern "C" void LLVMInitializeARMMCInstrInfo() { - RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget); - RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget); - - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); -} - -extern "C" void LLVMInitializeARMMCRegInfo() { - RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget); - RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget); - - TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); - TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); -} - -extern "C" void LLVMInitializeARMMCSubtargetInfo() { - RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheARMTarget); - RegisterMCSubtargetInfo<MCSubtargetInfo> Y(TheThumbTarget); - - TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, - createARMMCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, - createARMMCSubtargetInfo); -} - std::string ARM_MC::ParseARMTriple(StringRef TT) { // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. @@ -135,3 +82,47 @@ std::string ARM_MC::ParseARMTriple(StringRef TT) { return ARMArchFeature; } + +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + std::string ArchFS = ARM_MC::ParseARMTriple(TT); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS.str(); + else + ArchFS = FS; + } + + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitARMMCSubtargetInfo(X, CPU, ArchFS); + return X; +} + +MCInstrInfo *createARMMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitARMMCInstrInfo(X); + return X; +} + +MCRegisterInfo *createARMMCRegisterInfo() { + MCRegisterInfo *X = new MCRegisterInfo(); + InitARMMCRegisterInfo(X); + return X; +} + +// Force static initialization. +extern "C" void LLVMInitializeARMMCInstrInfo() { + RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget); + RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget); + + TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); +} + +extern "C" void LLVMInitializeARMMCRegInfo() { + RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget); + RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget); + + TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); + TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); +} diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h index 555430ea198..bc58634b16a 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -17,6 +17,7 @@ #include <string> namespace llvm { +class MCSubtargetInfo; class Target; class StringRef; @@ -24,6 +25,12 @@ extern Target TheARMTarget, TheThumbTarget; namespace ARM_MC { std::string ParseARMTriple(StringRef TT); + + /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. + /// This is exposed so Asm parser, etc. do not need to go through + /// TargetRegistry. + MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS); } } // End llvm namespace diff --git a/llvm/lib/Target/Alpha/AlphaSubtarget.cpp b/llvm/lib/Target/Alpha/AlphaSubtarget.cpp index 000f606acaf..75f5d8b4f91 100644 --- a/llvm/lib/Target/Alpha/AlphaSubtarget.cpp +++ b/llvm/lib/Target/Alpha/AlphaSubtarget.cpp @@ -14,9 +14,10 @@ #include "AlphaSubtarget.h" #include "Alpha.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "AlphaGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp index e854ccdf37f..b872fc63f23 100644 --- a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -27,7 +27,7 @@ extern "C" void LLVMInitializeAlphaTarget() { AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), DataLayout("e-f128:128:128-n64"), FrameLowering(Subtarget), Subtarget(TT, CPU, FS), diff --git a/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp b/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp index 696bb877595..7b3e4d7f8b5 100644 --- a/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp +++ b/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp @@ -13,9 +13,10 @@ #include "BlackfinSubtarget.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "BlackfinGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/Blackfin/BlackfinTargetMachine.cpp b/llvm/lib/Target/Blackfin/BlackfinTargetMachine.cpp index 477c43882f3..ee547e0a9c2 100644 --- a/llvm/lib/Target/Blackfin/BlackfinTargetMachine.cpp +++ b/llvm/lib/Target/Blackfin/BlackfinTargetMachine.cpp @@ -28,7 +28,7 @@ BlackfinTargetMachine::BlackfinTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), DataLayout("e-p:32:32-i64:32-f64:32-n32"), Subtarget(TT, CPU, FS), TLInfo(*this), diff --git a/llvm/lib/Target/CBackend/CTargetMachine.h b/llvm/lib/Target/CBackend/CTargetMachine.h index 88cc8eb56d1..e64216be0bd 100644 --- a/llvm/lib/Target/CBackend/CTargetMachine.h +++ b/llvm/lib/Target/CBackend/CTargetMachine.h @@ -22,7 +22,7 @@ namespace llvm { struct CTargetMachine : public TargetMachine { CTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : TargetMachine(T) {} + : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, diff --git a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp index cb94d281c66..d9835070fb0 100644 --- a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp +++ b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp @@ -13,12 +13,13 @@ #include "SPUSubtarget.h" #include "SPU.h" -#include "llvm/ADT/SmallVector.h" #include "SPURegisterInfo.h" +#include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "SPUGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp index f04e9824576..84c5fd7902e 100644 --- a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -36,7 +36,7 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, const std::string &CPU,const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), diff --git a/llvm/lib/Target/CppBackend/CPPTargetMachine.h b/llvm/lib/Target/CppBackend/CPPTargetMachine.h index 8023e1377c6..7322e3e34f0 100644 --- a/llvm/lib/Target/CppBackend/CPPTargetMachine.h +++ b/llvm/lib/Target/CppBackend/CPPTargetMachine.h @@ -24,7 +24,7 @@ class formatted_raw_ostream; struct CPPTargetMachine : public TargetMachine { CPPTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : TargetMachine(T) {} + : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, diff --git a/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp b/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp index 524f33d1933..603fc64bb9a 100644 --- a/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp +++ b/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp @@ -32,7 +32,6 @@ struct MBlazeOperand; class MBlazeAsmParser : public TargetAsmParser { MCAsmParser &Parser; - TargetMachine &TM; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -64,8 +63,9 @@ class MBlazeAsmParser : public TargetAsmParser { public: - MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {} + MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + MCAsmParser &_Parser) + : TargetAsmParser(T), Parser(_Parser) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands); diff --git a/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp b/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp index 8e706cd4c73..eb5e28f131d 100644 --- a/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp +++ b/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp @@ -16,9 +16,10 @@ #include "MBlazeRegisterInfo.h" #include "llvm/Support/CommandLine.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "MBlazeGenSubtargetInfo.inc" using namespace llvm; @@ -61,4 +62,3 @@ enablePostRAScheduler(CodeGenOpt::Level OptLevel, CriticalPathRCs.push_back(&MBlaze::GPRRegClass); return HasItin && OptLevel >= CodeGenOpt::Default; } - diff --git a/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp b/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp index 1cbd2d413b1..c18cb8be7d8 100644 --- a/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp +++ b/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp @@ -81,7 +81,7 @@ extern "C" void LLVMInitializeMBlazeTarget() { MBlazeTargetMachine:: MBlazeTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS): - LLVMTargetMachine(T, TT), + LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), diff --git a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp index 42cc8822958..dddfd2c70c2 100644 --- a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp +++ b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp @@ -14,9 +14,10 @@ #include "MSP430Subtarget.h" #include "MSP430.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "MSP430GenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index 3ee5e6ac210..ecce11e8fd6 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -30,7 +30,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 7a5d417ce64..a0cb71ee6d6 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -14,9 +14,10 @@ #include "MipsSubtarget.h" #include "Mips.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "MipsGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 88ce3b88194..efbb767955e 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -37,7 +37,7 @@ MipsTargetMachine:: MipsTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool isLittle=false): - LLVMTargetMachine(T, TT), + LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, isLittle), DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : diff --git a/llvm/lib/Target/PTX/PTXSubtarget.cpp b/llvm/lib/Target/PTX/PTXSubtarget.cpp index 846eee1792d..584c1d0295e 100644 --- a/llvm/lib/Target/PTX/PTXSubtarget.cpp +++ b/llvm/lib/Target/PTX/PTXSubtarget.cpp @@ -14,9 +14,10 @@ #include "PTXSubtarget.h" #include "llvm/Support/ErrorHandling.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "PTXGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/PTX/PTXTargetMachine.cpp b/llvm/lib/Target/PTX/PTXTargetMachine.cpp index ef648c639f3..caeb851657f 100644 --- a/llvm/lib/Target/PTX/PTXTargetMachine.cpp +++ b/llvm/lib/Target/PTX/PTXTargetMachine.cpp @@ -55,7 +55,7 @@ PTXTargetMachine::PTXTargetMachine(const Target &T, const std::string &CPU, const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), DataLayout(is64Bit ? DataLayout64 : DataLayout32), Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index 7eeeaf59ecc..d4861256a8c 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -17,9 +17,10 @@ #include "llvm/Target/TargetMachine.h" #include <cstdlib> -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "PPCGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 09fc1e3df87..8dad9423716 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -69,7 +69,7 @@ extern "C" void LLVMInitializePowerPCTarget() { PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit), diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp index c8281ceaaf9..05cea2af0ce 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -13,9 +13,10 @@ #include "SparcSubtarget.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "SparcGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 792dd94c334..48a6e97e925 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -32,7 +32,7 @@ extern "C" void LLVMInitializeSparcTarget() { SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool is64bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index 518c09f2602..f20010b2b2b 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -16,9 +16,10 @@ #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "SystemZGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index 3329ce661c5..86e97e4ea3a 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -26,7 +26,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index 14044f25a0b..74a1f4e8da5 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -216,8 +216,9 @@ FunctionSections("ffunction-sections", // TargetMachine Class // -TargetMachine::TargetMachine(const Target &T) - : TheTarget(T), AsmInfo(0), +TargetMachine::TargetMachine(const Target &T, + StringRef TT, StringRef CPU, StringRef FS) + : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0), MCRelaxAll(false), MCNoExecStack(false), MCSaveTempLabels(false), diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 4738b2773f4..45b1944997f 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -15,6 +15,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" @@ -25,6 +26,10 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" + +#define GET_SUBTARGETINFO_ENUM +#include "X86GenSubtargetInfo.inc" + using namespace llvm; namespace { @@ -32,10 +37,7 @@ struct X86Operand; class X86ATTAsmParser : public TargetAsmParser { MCAsmParser &Parser; - TargetMachine &TM; - -protected: - unsigned Is64Bit : 1; + MCSubtargetInfo *STI; private: MCAsmParser &getParser() const { return Parser; } @@ -61,6 +63,11 @@ private: /// or %es:(%edi) in 32bit mode. bool isDstOp(X86Operand &Op); + bool is64Bit() { + // FIXME: Can tablegen auto-generate this? + return (STI->getFeatureBits() & X86::Mode64Bit) != 0; + } + /// @name Auto-generated Matcher Functions /// { @@ -70,12 +77,13 @@ private: /// } public: - X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM) - : TargetAsmParser(T), Parser(parser), TM(TM) { + X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS, + MCAsmParser &parser) + : TargetAsmParser(T), Parser(parser) { + STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS); // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures( - &TM.getSubtarget<X86Subtarget>())); + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); } virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); @@ -84,23 +92,6 @@ public: virtual bool ParseDirective(AsmToken DirectiveID); }; - -class X86_32ATTAsmParser : public X86ATTAsmParser { -public: - X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM) - : X86ATTAsmParser(T, Parser, TM) { - Is64Bit = false; - } -}; - -class X86_64ATTAsmParser : public X86ATTAsmParser { -public: - X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM) - : X86ATTAsmParser(T, Parser, TM) { - Is64Bit = true; - } -}; - } // end anonymous namespace /// @name Auto-generated Match Functions @@ -365,7 +356,7 @@ struct X86Operand : public MCParsedAsmOperand { } // end anonymous namespace. bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { - unsigned basereg = Is64Bit ? X86::RSI : X86::ESI; + unsigned basereg = is64Bit() ? X86::RSI : X86::ESI; return (Op.isMem() && (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && @@ -375,7 +366,7 @@ bool X86ATTAsmParser::isSrcOp(X86Operand &Op) { } bool X86ATTAsmParser::isDstOp(X86Operand &Op) { - unsigned basereg = Is64Bit ? X86::RDI : X86::EDI; + unsigned basereg = is64Bit() ? X86::RDI : X86::EDI; return Op.isMem() && Op.Mem.SegReg == X86::ES && isa<MCConstantExpr>(Op.Mem.Disp) && @@ -406,7 +397,7 @@ bool X86ATTAsmParser::ParseRegister(unsigned &RegNo, // FIXME: This should be done using Requires<In32BitMode> and // Requires<In64BitMode> so "eiz" usage in 64-bit instructions // can be also checked. - if (RegNo == X86::RIZ && !Is64Bit) + if (RegNo == X86::RIZ && !is64Bit()) return Error(Tok.getLoc(), "riz register in 64-bit mode only"); // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. @@ -826,7 +817,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]" if (Name.startswith("movs") && Operands.size() == 3 && (Name == "movsb" || Name == "movsw" || Name == "movsl" || - (Is64Bit && Name == "movsq"))) { + (is64Bit() && Name == "movsq"))) { X86Operand &Op = *(X86Operand*)Operands.begin()[1]; X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; if (isSrcOp(Op) && isDstOp(Op2)) { @@ -839,7 +830,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]" if (Name.startswith("lods") && Operands.size() == 3 && (Name == "lods" || Name == "lodsb" || Name == "lodsw" || - Name == "lodsl" || (Is64Bit && Name == "lodsq"))) { + Name == "lodsl" || (is64Bit() && Name == "lodsq"))) { X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); if (isSrcOp(*Op1) && Op2->isReg()) { @@ -869,7 +860,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]" if (Name.startswith("stos") && Operands.size() == 3 && (Name == "stos" || Name == "stosb" || Name == "stosw" || - Name == "stosl" || (Is64Bit && Name == "stosq"))) { + Name == "stosl" || (is64Bit() && Name == "stosq"))) { X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); if (isDstOp(*Op2) && Op1->isReg()) { @@ -1144,8 +1135,8 @@ extern "C" void LLVMInitializeX86AsmLexer(); // Force static initialization. extern "C" void LLVMInitializeX86AsmParser() { - RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target); - RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target); + RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target); + RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target); LLVMInitializeX86AsmLexer(); } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 4d7dbb875e4..bcde60a0532 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -25,6 +25,7 @@ #define GET_INSTRINFO_MC_DESC #include "X86GenInstrInfo.inc" +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #include "X86GenSubtargetInfo.inc" @@ -35,7 +36,7 @@ std::string X86_MC::ParseX86Triple(StringRef TT) { Triple TheTriple(TT); if (TheTriple.getArch() == Triple::x86_64) return "+64bit-mode"; - return ""; + return "-64bit-mode"; } /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the @@ -128,20 +129,8 @@ static bool hasX86_64() { return false; } -MCInstrInfo *createX86MCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitX86MCInstrInfo(X); - return X; -} - -MCRegisterInfo *createX86MCRegisterInfo() { - MCRegisterInfo *X = new MCRegisterInfo(); - InitX86MCRegisterInfo(X); - return X; -} - -MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { std::string ArchFS = X86_MC::ParseX86Triple(TT); if (!FS.empty()) { if (!ArchFS.empty()) @@ -159,7 +148,19 @@ MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, ArchFS = "+64bit-mode"; MCSubtargetInfo *X = new MCSubtargetInfo(); - InitX86MCSubtargetInfo(X, CPU, ArchFS); + InitX86MCSubtargetInfo(X, CPUName, ArchFS); + return X; +} + +MCInstrInfo *createX86MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitX86MCInstrInfo(X); + return X; +} + +MCRegisterInfo *createX86MCRegisterInfo() { + MCRegisterInfo *X = new MCRegisterInfo(); + InitX86MCRegisterInfo(X); return X; } @@ -179,13 +180,3 @@ extern "C" void LLVMInitializeX86MCRegInfo() { TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); } - -extern "C" void LLVMInitializeX86MCSubtargetInfo() { - RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheX86_32Target); - RegisterMCSubtargetInfo<MCSubtargetInfo> Y(TheX86_64Target); - - TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, - createX86MCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, - createX86MCSubtargetInfo); -} diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h index 17c905227a7..5294a4fa5b5 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -17,6 +17,7 @@ #include <string> namespace llvm { +class MCSubtargetInfo; class Target; class StringRef; @@ -31,9 +32,17 @@ namespace X86_MC { unsigned *rEBX, unsigned *rECX, unsigned *rEDX); void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); + + /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance. + /// This is exposed so Asm parser, etc. do not need to go through + /// TargetRegistry. + MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS); } + } // End llvm namespace + // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 1982df50510..e89884ed2e6 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -438,8 +438,10 @@ def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; def FPStackf32 : Predicate<"!Subtarget->hasXMM()">; def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">; -def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate; -def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate; +def In32BitMode : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<"!Mode64Bit">; +def In64BitMode : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<"Mode64Bit">; def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index cba048482ea..b567c456b8f 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -21,9 +21,10 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "X86GenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index aaf15fdee7a..26c0d548620 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -119,7 +119,7 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT, X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS, StackAlignmentOverride), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { diff --git a/llvm/lib/Target/XCore/XCoreSubtarget.cpp b/llvm/lib/Target/XCore/XCoreSubtarget.cpp index c727183c9a4..7d8fe8a10b2 100644 --- a/llvm/lib/Target/XCore/XCoreSubtarget.cpp +++ b/llvm/lib/Target/XCore/XCoreSubtarget.cpp @@ -14,9 +14,10 @@ #include "XCoreSubtarget.h" #include "XCore.h" -#define GET_SUBTARGETINFO_CTOR +#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "XCoreGenSubtargetInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index 542038b297a..f2bea33f358 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -23,7 +23,7 @@ using namespace llvm; XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT, const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), + : LLVMTargetMachine(T, TT, CPU, FS), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), |
