diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 21 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSubtarget.h | 10 |
4 files changed, 40 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index 84ae0eddf98..1731afc1961 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -243,6 +243,8 @@ let DecoderNamespace = "MicroMipsFP64" in { MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64; def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64; + def MTC1_D64_MM : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, + MFC1_FM_MM<0xa0>, ISA_MICROMIPS, FGR_64; } let DecoderNamespace = "MicroMips" in { @@ -405,6 +407,9 @@ let AddedComplexity = 40 in { def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; } +def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), + (MTC1_D64_MM GPR32Opnd:$src)>, ISA_MICROMIPS, FGR_64; + def : MipsPat<(f32 fpimm0), (MTC1_MM ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6; def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM ZERO))>, ISA_MICROMIPS32_NOT_MIPS32R6; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index ebadb59a043..9f914bb9e87 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1116,6 +1116,27 @@ let DecoderNamespace = "MicroMips" in { ISA_MICROMIPS32_NOT_MIPS32R6; } +let AdditionalPredicates = [NotDSP] in { + def PseudoMULT_MM : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMULTu_MM : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMFHI_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMFLO_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMTLOHI_MM : PseudoMTLOHI<ACC64, GPR32>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMADDU_MM : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMSUB_MM : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMSUBU_MM : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>, + ISA_MICROMIPS32_NOT_MIPS32R6; +} + def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6; def TAILCALLREG_MM : TailCallReg<JRC16_MM, GPR32Opnd>, diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index b1f2660a368..c7ab90ed2a3 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -421,12 +421,16 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { expandERet(MBB, MI); break; case Mips::PseudoMFHI: - Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; - expandPseudoMFHiLo(MBB, MI, Opc); + expandPseudoMFHiLo(MBB, MI, Mips::MFHI); + break; + case Mips::PseudoMFHI_MM: + expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM); break; case Mips::PseudoMFLO: - Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; - expandPseudoMFHiLo(MBB, MI, Opc); + expandPseudoMFHiLo(MBB, MI, Mips::MFLO); + break; + case Mips::PseudoMFLO_MM: + expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM); break; case Mips::PseudoMFHI64: expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h index 896dd0eb0a5..ad8f4848b87 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.h +++ b/llvm/lib/Target/Mips/MipsSubtarget.h @@ -295,8 +295,10 @@ public: bool inMips16HardFloat() const { return inMips16Mode() && InMips16HardFloat; } - bool inMicroMipsMode() const { return InMicroMipsMode; } - bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } + bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; } + bool inMicroMips32r6Mode() const { + return inMicroMipsMode() && hasMips32r6(); + } bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } bool hasDSPR3() const { return HasDSPR3; } @@ -312,14 +314,14 @@ public: } bool useSmallSection() const { return UseSmallSection; } - bool hasStandardEncoding() const { return !inMips16Mode(); } + bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; } bool useSoftFloat() const { return IsSoftFloat; } bool useLongCalls() const { return UseLongCalls; } bool enableLongBranchPass() const { - return hasStandardEncoding() || allowMixed16_32(); + return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32(); } /// Features related to the presence of specific instructions. |
