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-rw-r--r--llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp126
-rw-r--r--llvm/lib/Target/X86/X86InstrAVX512.td57
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td4
-rw-r--r--llvm/lib/Target/X86/X86IntrinsicsInfo.h28
4 files changed, 107 insertions, 108 deletions
diff --git a/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp b/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
index 10b09c23a2d..db981edb27b 100644
--- a/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
@@ -16,31 +16,11 @@
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "Utils/X86ShuffleDecode.h"
#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-static unsigned getVectorRegSize(unsigned RegNo) {
- if (X86MCRegisterClasses[X86::VR512RegClassID].contains(RegNo))
- return 512;
- else if (X86MCRegisterClasses[X86::VR256XRegClassID].contains(RegNo))
- return 256;
- else if (X86MCRegisterClasses[X86::VR128XRegClassID].contains(RegNo))
- return 128;
-
- llvm_unreachable("Unknown vector reg!");
- return 0;
-}
-
-static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
- unsigned OperandIndex) {
- unsigned OpReg = MI->getOperand(OperandIndex).getReg();
- return MVT::getVectorVT(ScalarVT,
- getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
-}
-
/// \brief Extracts the src/dst types for a given zero extension instruction.
/// \note While the number of elements in DstVT type correct, the
/// number in the SrcVT type is expanded to fill the src xmm register and the
@@ -127,30 +107,19 @@ static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
}
}
-#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
- case X86::V##Inst##Suffix##src: \
- case X86::V##Inst##Suffix##src##k: \
- case X86::V##Inst##Suffix##src##kz:
-
-#define CASE_SSE_INS_COMMON(Inst, src) \
- case X86::Inst##src:
-
-#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
- case X86::V##Inst##Suffix##src:
-
-#define CASE_MOVDUP(Inst, src) \
- CASE_MASK_INS_COMMON(Inst, Z, r##src) \
- CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
- CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
- CASE_AVX_INS_COMMON(Inst, , r##src) \
- CASE_AVX_INS_COMMON(Inst, Y, r##src) \
- CASE_SSE_INS_COMMON(Inst, r##src) \
+#define CASE_VSHUF_COMMON(Inst, Suffix, src2) \
+ case X86::VSHUFF##Inst##Suffix##r##src2##i: \
+ case X86::VSHUFF##Inst##Suffix##r##src2##ik: \
+ case X86::VSHUFF##Inst##Suffix##r##src2##ikz: \
+ case X86::VSHUFI##Inst##Suffix##r##src2##i: \
+ case X86::VSHUFI##Inst##Suffix##r##src2##ik: \
+ case X86::VSHUFI##Inst##Suffix##r##src2##ikz:
-#define CASE_VSHUF(Inst, src) \
- CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
- CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
- CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
- CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
+#define CASE_VSHUF(Inst) \
+ CASE_VSHUF_COMMON(Inst, Z, r) \
+ CASE_VSHUF_COMMON(Inst, Z, m) \
+ CASE_VSHUF_COMMON(Inst, Z256, r) \
+ CASE_VSHUF_COMMON(Inst, Z256, m) \
/// \brief Extracts the types and if it has memory operand for a given
/// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
@@ -160,15 +129,25 @@ static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
default:
llvm_unreachable("Unknown VSHUF64x2 family instructions.");
break;
- CASE_VSHUF(64X2, m)
+ CASE_VSHUF_COMMON(64X2, Z, m)
HasMemOp = true; // FALL THROUGH.
- CASE_VSHUF(64X2, r)
- VT = getRegOperandVectorVT(MI, MVT::i64, 0);
+ CASE_VSHUF_COMMON(64X2, Z, r)
+ VT = MVT::v8i64;
break;
- CASE_VSHUF(32X4, m)
+ CASE_VSHUF_COMMON(64X2, Z256, m)
HasMemOp = true; // FALL THROUGH.
- CASE_VSHUF(32X4, r)
- VT = getRegOperandVectorVT(MI, MVT::i32, 0);
+ CASE_VSHUF_COMMON(64X2, Z256, r)
+ VT = MVT::v4i64;
+ break;
+ CASE_VSHUF_COMMON(32X4, Z, m)
+ HasMemOp = true; // FALL THROUGH.
+ CASE_VSHUF_COMMON(32X4, Z, r)
+ VT = MVT::v16i32;
+ break;
+ CASE_VSHUF_COMMON(32X4, Z256, m)
+ HasMemOp = true; // FALL THROUGH.
+ CASE_VSHUF_COMMON(32X4, Z256, r)
+ VT = MVT::v8i32;
break;
}
}
@@ -318,24 +297,43 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
DestName = getRegName(MI->getOperand(0).getReg());
DecodeMOVHLPSMask(2, ShuffleMask);
break;
- CASE_MOVDUP(MOVSLDUP, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+
+ case X86::MOVSLDUPrr:
+ case X86::VMOVSLDUPrr:
+ Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
- CASE_MOVDUP(MOVSLDUP, m) {
- MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
+ case X86::MOVSLDUPrm:
+ case X86::VMOVSLDUPrm:
DestName = getRegName(MI->getOperand(0).getReg());
- DecodeMOVSLDUPMask(VT, ShuffleMask);
+ DecodeMOVSLDUPMask(MVT::v4f32, ShuffleMask);
break;
- }
- CASE_MOVDUP(MOVSHDUP, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+
+ case X86::VMOVSHDUPYrr:
+ Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
- CASE_MOVDUP(MOVSHDUP, m) {
- MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
+ case X86::VMOVSHDUPYrm:
DestName = getRegName(MI->getOperand(0).getReg());
- DecodeMOVSHDUPMask(VT, ShuffleMask);
+ DecodeMOVSHDUPMask(MVT::v8f32, ShuffleMask);
break;
- }
+
+ case X86::VMOVSLDUPYrr:
+ Src1Name = getRegName(MI->getOperand(1).getReg());
+ // FALL THROUGH.
+ case X86::VMOVSLDUPYrm:
+ DestName = getRegName(MI->getOperand(0).getReg());
+ DecodeMOVSLDUPMask(MVT::v8f32, ShuffleMask);
+ break;
+
+ case X86::MOVSHDUPrr:
+ case X86::VMOVSHDUPrr:
+ Src1Name = getRegName(MI->getOperand(1).getReg());
+ // FALL THROUGH.
+ case X86::MOVSHDUPrm:
+ case X86::VMOVSHDUPrm:
+ DestName = getRegName(MI->getOperand(0).getReg());
+ DecodeMOVSHDUPMask(MVT::v4f32, ShuffleMask);
+ break;
+
case X86::VMOVDDUPYrr:
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
@@ -773,10 +771,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
break;
- CASE_VSHUF(64X2, r)
- CASE_VSHUF(64X2, m)
- CASE_VSHUF(32X4, r)
- CASE_VSHUF(32X4, m) {
+ CASE_VSHUF(64X2)
+ CASE_VSHUF(32X4) {
MVT VT;
bool HasMemOp;
unsigned NumOp = MI->getNumOperands();
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 132952f4735..1dde04d4f7e 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -4254,6 +4254,35 @@ defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
(VMOVDDUPZrm addr:$src)>;
+//===---------------------------------------------------------------------===//
+// Replicate Single FP - MOVSHDUP and MOVSLDUP
+//===---------------------------------------------------------------------===//
+multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
+ ValueType vt, RegisterClass RC, PatFrag mem_frag,
+ X86MemOperand x86memop> {
+ def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
+ let mayLoad = 1 in
+ def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
+}
+
+defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
+ v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
+ EVEX_CD8<32, CD8VF>;
+defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
+ v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
+ EVEX_CD8<32, CD8VF>;
+
+def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
+def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
+ (VMOVSHDUPZrm addr:$src)>;
+def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
+def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
+ (VMOVSLDUPZrm addr:$src)>;
+
//===----------------------------------------------------------------------===//
// Move Low to High and High to Low packed FP Instructions
//===----------------------------------------------------------------------===//
@@ -7027,13 +7056,13 @@ defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
X86VectorVTInfo _> {
defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
- (ins _.RC:$src1), OpcodeStr,
+ (ins _.RC:$src1), OpcodeStr##_.Suffix,
"$src1", "$src1",
(_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
let mayLoad = 1 in
defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.MemOp:$src1), OpcodeStr,
+ (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
"$src1", "$src1",
(_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
@@ -7044,7 +7073,7 @@ multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
let mayLoad = 1 in
defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.ScalarMemOp:$src1), OpcodeStr,
+ (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
"${src1}"##_.BroadcastStr,
"${src1}"##_.BroadcastStr,
(_.VT (OpNode (X86VBroadcast
@@ -7081,16 +7110,15 @@ multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
SDNode OpNode, Predicate prd> {
- defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
+ defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
prd>, VEX_W;
- defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
- prd>;
+ defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
}
multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
SDNode OpNode, Predicate prd> {
- defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
- defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
+ defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
+ defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
}
multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
@@ -7124,19 +7152,6 @@ multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
-//===---------------------------------------------------------------------===//
-// Replicate Single FP - MOVSHDUP and MOVSLDUP
-//===---------------------------------------------------------------------===//
-multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
- defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
- HasAVX512>, XS;
- let isCodeGenOnly = 1 in
- defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
- HasAVX512>, XS;
-}
-
-defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
-defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
//===----------------------------------------------------------------------===//
// AVX-512 - Unpack Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index f39fa3f617a..1407be2f60c 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -5135,7 +5135,7 @@ def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
}
-let Predicates = [HasAVX, NoVLX] in {
+let Predicates = [HasAVX] in {
defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
v4f32, VR128, loadv4f32, f128mem>, VEX;
defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
@@ -5150,7 +5150,7 @@ defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
memopv4f32, f128mem>;
-let Predicates = [HasAVX, NoVLX] in {
+let Predicates = [HasAVX] in {
def : Pat<(v4i32 (X86Movshdup VR128:$src)),
(VMOVSHDUPrr VR128:$src)>;
def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 337c46c56c8..7e7dc3a9e61 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -776,10 +776,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx512_mask_max_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FMAX, 0),
X86_INTRINSIC_DATA(avx512_mask_max_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMAX,
X86ISD::FMAX_RND),
- X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK_RM,
- X86ISD::FMAX, X86ISD::FMAX_RND),
- X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK_RM,
- X86ISD::FMAX, X86ISD::FMAX_RND),
+ X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMAX,
+ X86ISD::FMAX_RND),
+ X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMAX,
+ X86ISD::FMAX_RND),
X86_INTRINSIC_DATA(avx512_mask_min_pd_128, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
X86_INTRINSIC_DATA(avx512_mask_min_pd_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
X86_INTRINSIC_DATA(avx512_mask_min_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
@@ -788,22 +788,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx512_mask_min_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
X86_INTRINSIC_DATA(avx512_mask_min_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
X86ISD::FMIN_RND),
- X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK_RM,
- X86ISD::FMIN, X86ISD::FMIN_RND),
- X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK_RM,
- X86ISD::FMIN, X86ISD::FMIN_RND),
- X86_INTRINSIC_DATA(avx512_mask_movshdup_128, INTR_TYPE_1OP_MASK,
- X86ISD::MOVSHDUP, 0),
- X86_INTRINSIC_DATA(avx512_mask_movshdup_256, INTR_TYPE_1OP_MASK,
- X86ISD::MOVSHDUP, 0),
- X86_INTRINSIC_DATA(avx512_mask_movshdup_512, INTR_TYPE_1OP_MASK,
- X86ISD::MOVSHDUP, 0),
- X86_INTRINSIC_DATA(avx512_mask_movsldup_128, INTR_TYPE_1OP_MASK,
- X86ISD::MOVSLDUP, 0),
- X86_INTRINSIC_DATA(avx512_mask_movsldup_256, INTR_TYPE_1OP_MASK,
- X86ISD::MOVSLDUP, 0),
- X86_INTRINSIC_DATA(avx512_mask_movsldup_512, INTR_TYPE_1OP_MASK,
- X86ISD::MOVSLDUP, 0),
+ X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMIN,
+ X86ISD::FMIN_RND),
+ X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMIN,
+ X86ISD::FMIN_RND),
X86_INTRINSIC_DATA(avx512_mask_mul_pd_128, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
X86_INTRINSIC_DATA(avx512_mask_mul_pd_256, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
X86_INTRINSIC_DATA(avx512_mask_mul_pd_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
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