diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 34 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600Schedule.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIDefines.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 28 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VIInstructions.td | 2 |
10 files changed, 40 insertions, 40 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index 4b6fc47cdb7..4fb8aea4876 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -30,7 +30,7 @@ class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instructio field bits<64> SoftFail = 0; let DecoderNamespace = Namespace; - + let TSFlags{63} = isRegisterLoad; let TSFlags{62} = isRegisterStore; } diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index f3fd71d3f23..1abc9bc9e9e 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -124,7 +124,7 @@ public: void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const { if (Imm.Type == ImmTyNone && ApplyModifiers && Imm.Modifiers != 0) { - // Apply modifiers to immediate value + // Apply modifiers to immediate value int64_t Val = Imm.Val; bool Negate = Imm.Modifiers & 0x1; bool Abs = Imm.Modifiers & 0x2; @@ -562,7 +562,7 @@ public: MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); return static_cast<AMDGPUTargetStreamer &>(TS); } - + void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; } void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; } void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; } @@ -638,10 +638,10 @@ public: AMDGPUOperand::Ptr defaultLWE() const; AMDGPUOperand::Ptr defaultSMRDOffset() const; AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const; - + AMDGPUOperand::Ptr defaultClampSI() const; AMDGPUOperand::Ptr defaultOModSI() const; - + OperandMatchResultTy parseOModOperand(OperandVector &Operands); void cvtId(MCInst &Inst, const OperandVector &Operands); @@ -943,7 +943,7 @@ AMDGPUAsmParser::parseImm(OperandVector &Operands) { if (Minus) F.changeSign(); Operands.push_back( - AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S, + AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S, AMDGPUOperand::ImmTyNone, true)); return MatchOperand_Success; } @@ -970,7 +970,7 @@ AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) { AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseRegOrImmWithInputMods(OperandVector &Operands) { - // XXX: During parsing we can't determine if minus sign means + // XXX: During parsing we can't determine if minus sign means // negate-modifier or negative immediate value. // By default we suppose it is modifier. bool Negate = false, Abs = false, Abs2 = false; @@ -1024,7 +1024,7 @@ AMDGPUAsmParser::parseRegOrImmWithInputMods(OperandVector &Operands) { Parser.Lex(); Modifiers |= 0x2; } - + if (Modifiers) { AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back()); Op.setModifiers(Modifiers); @@ -1403,23 +1403,23 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info, // Add the instruction mnemonic Name = parseMnemonicSuffix(Name); Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc)); - + while (!getLexer().is(AsmToken::EndOfStatement)) { AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name); // Eat the comma or space if there is one. if (getLexer().is(AsmToken::Comma)) Parser.Lex(); - + switch (Res) { case MatchOperand_Success: break; - case MatchOperand_ParseFail: + case MatchOperand_ParseFail: Error(getLexer().getLoc(), "failed parsing operand."); while (!getLexer().is(AsmToken::EndOfStatement)) { Parser.Lex(); } return true; - case MatchOperand_NoMatch: + case MatchOperand_NoMatch: Error(getLexer().getLoc(), "not a valid operand."); while (!getLexer().is(AsmToken::EndOfStatement)) { Parser.Lex(); @@ -1527,7 +1527,7 @@ void addOptionalImmOperand(MCInst& Inst, const OperandVector& Operands, } } -AMDGPUAsmParser::OperandMatchResultTy +AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) { if (getLexer().isNot(AsmToken::Identifier)) { return MatchOperand_NoMatch; @@ -1541,7 +1541,7 @@ AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) { if (getLexer().isNot(AsmToken::Colon)) { return MatchOperand_ParseFail; } - + Parser.Lex(); if (getLexer().isNot(AsmToken::Identifier)) { return MatchOperand_ParseFail; @@ -2538,12 +2538,12 @@ AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix, SMLoc S = Parser.getTok().getLoc(); StringRef Value; AMDGPUAsmParser::OperandMatchResultTy res; - + res = parseStringWithPrefix(Prefix, Value); if (res != MatchOperand_Success) { return res; } - + int64_t Int; Int = StringSwitch<int64_t>(Value) .Case("BYTE_0", 0) @@ -2564,7 +2564,7 @@ AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix, return MatchOperand_Success; } -AMDGPUAsmParser::OperandMatchResultTy +AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); StringRef Value; @@ -2688,7 +2688,7 @@ extern "C" void LLVMInitializeAMDGPUAsmParser() { unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) { // Tokens like "glc" would be parsed as immediate operands in ParseOperand(). - // But MatchInstructionImpl() expects to meet token and fails to validate + // But MatchInstructionImpl() expects to meet token and fails to validate // operand. This method checks if we are given immediate operand but expect to // get corresponding token. AMDGPUOperand &Operand = (AMDGPUOperand&)Op; diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index f96bb5e4c77..e11de855fe5 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -124,7 +124,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, do { // ToDo: better to switch encoding length using some bit predicate // but it is unknown yet, so try all we can - + // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 // encodings if (Bytes.size() >= 8) { diff --git a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp index 96f72875194..560e2e21224 100644 --- a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp @@ -512,7 +512,7 @@ public: std::vector<ClauseFile> FetchClauses, AluClauses; std::vector<MachineInstr *> LastAlu(1); std::vector<MachineInstr *> ToPopAfter; - + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) { if (TII->usesTextureCache(I) || TII->usesVertexCache(I)) { @@ -614,7 +614,7 @@ public: DEBUG(dbgs() << CfCount << ":"; MIb->dump();); CfCount++; } - + MachineInstr *IfOrElseInst = IfThenElseStack.back(); IfThenElseStack.pop_back(); CounterPropagateAddr(IfOrElseInst, CfCount); diff --git a/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp b/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp index fdc20302f4a..8c690a7613c 100644 --- a/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp +++ b/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp @@ -276,7 +276,7 @@ private: BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode)) // We don't use the ADDR field until R600ControlFlowFinalizer pass, where // it is safe to assume it is 0. However if we always put 0 here, the ifcvt - // pass may assume that identical ALU clause starter at the beginning of a + // pass may assume that identical ALU clause starter at the beginning of a // true and false branch can be factorized which is not the case. .addImm(Address++) // ADDR .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0 diff --git a/llvm/lib/Target/AMDGPU/R600Schedule.td b/llvm/lib/Target/AMDGPU/R600Schedule.td index df62bf85c0a..70fb46c1a7d 100644 --- a/llvm/lib/Target/AMDGPU/R600Schedule.td +++ b/llvm/lib/Target/AMDGPU/R600Schedule.td @@ -9,7 +9,7 @@ // // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS -// slot has been removed. +// slot has been removed. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp index f8c7fb9fdb4..5f182c5304c 100644 --- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp @@ -320,7 +320,7 @@ Value *SIAnnotateControlFlow::handleLoopCondition(Value *Cond, PHINode *Broken, } else { llvm_unreachable("Unhandled loop condition!"); } - return 0; + return nullptr; } /// \brief Handle a back edge (loop) diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 8dcfc8a8942..e1ca8b1dc48 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -239,7 +239,7 @@ enum WidthMinusOne { // WidthMinusOne, (5) [15:11] #define C_00B84C_LDS_SIZE 0xFF007FFF #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) -#define C_00B84C_EXCP_EN +#define C_00B84C_EXCP_EN #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 7f4757ba281..e5e82031f50 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -38,8 +38,8 @@ using namespace llvm; // -amdgpu-fast-fdiv - Command line option to enable faster 2.5 ulp fdiv. static cl::opt<bool> EnableAMDGPUFastFDIV( - "amdgpu-fast-fdiv", - cl::desc("Enable faster 2.5 ulp fdiv"), + "amdgpu-fast-fdiv", + cl::desc("Enable faster 2.5 ulp fdiv"), cl::init(false)); static unsigned findFirstFreeSGPR(CCState &CCInfo) { @@ -492,7 +492,7 @@ static bool isFlatGlobalAddrSpace(unsigned AS) { bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const { - return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS); + return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS); } @@ -1989,32 +1989,32 @@ SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const { SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0); return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul); - } - + } + // Generates more precise fpdiv32. const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); - + SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1); - + SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, RHS, RHS, LHS); SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, LHS, RHS, LHS); - + SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, DenominatorScaled); - + SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, DenominatorScaled); - + SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, ApproxRcp, One); SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, ApproxRcp); - + SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, NumeratorScaled, Fma1); - + SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, NumeratorScaled); SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul); SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, NumeratorScaled); - + SDValue Scale = NumeratorScaled.getValue(1); SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32, Fma4, Fma1, Fma3, Scale); - + return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS); } diff --git a/llvm/lib/Target/AMDGPU/VIInstructions.td b/llvm/lib/Target/AMDGPU/VIInstructions.td index dd85fb194f7..fcaa00d6f73 100644 --- a/llvm/lib/Target/AMDGPU/VIInstructions.td +++ b/llvm/lib/Target/AMDGPU/VIInstructions.td @@ -121,7 +121,7 @@ def : Pat < //===----------------------------------------------------------------------===// def : Pat < - (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask, + (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask, imm:$bound_ctrl), (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask), (as_i32imm $bank_mask), (as_i1imm $bound_ctrl)) |
