8 files changed, 13 insertions, 20 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 1f342ee5622..20015ae82fd 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -367,7 +367,7 @@ unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
     RC = TRI.getMinimalPhysRegClass(Reg);
   } else {
     LLT Ty = MRI.getType(Reg);
-    unsigned RegSize = Ty.isSized() ? Ty.getSizeInBits() : 0;
+    unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
     // If Reg is not a generic register, query the register class to
     // get its size.
     if (RegSize)
diff --git a/llvm/lib/CodeGen/LowLevelType.cpp b/llvm/lib/CodeGen/LowLevelType.cpp
index 819d85aae5b..fd235f2cfd1 100644
--- a/llvm/lib/CodeGen/LowLevelType.cpp
+++ b/llvm/lib/CodeGen/LowLevelType.cpp
@@ -35,7 +35,7 @@ LLT::LLT(Type &Ty, const DataLayout &DL) {
     ElementsOrAddrSpace = 1;
     assert(SizeInBits != 0 && "invalid zero-sized type");
   } else {
-    Kind = Unsized;
+    Kind = Invalid;
     SizeInBits = ElementsOrAddrSpace = 0;
   }
 }
@@ -45,10 +45,9 @@ void LLT::print(raw_ostream &OS) const {
     OS << "<" << ElementsOrAddrSpace << " x s" << SizeInBits << ">";
   else if (isPointer())
     OS << "p" << getAddressSpace();
-  else if (isSized())
+  else if (isValid()) {
+    assert(isScalar() && "unexpected type");
     OS << "s" << getScalarSizeInBits();
-  else if (isValid())
-    OS << "unsized";
-  else
+  } else
     llvm_unreachable("trying to print an invalid type");
 }
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 6fb3d281be0..2f4410ba7cd 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1039,11 +1039,7 @@ bool MIParser::parseIRConstant(StringRef::iterator Loc, const Constant *&C) {
 }
 
 bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
-  if (Token.is(MIToken::Identifier) && Token.stringValue() == "unsized") {
-    lex();
-    Ty = LLT::unsized();
-    return false;
-  } else if (Token.is(MIToken::ScalarType)) {
+  if (Token.is(MIToken::ScalarType)) {
     Ty = LLT::scalar(APSInt(Token.range().drop_front()).getZExtValue());
     lex();
     return false;
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index ca89a1ff7bc..55306dd6727 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -143,7 +143,7 @@ void MachineRegisterInfo::clearVirtRegTypes() {
   // Verify that the size of the now-constrained vreg is unchanged.
   for (auto &VRegToType : getVRegToType()) {
     auto *RC = getRegClass(VRegToType.first);
-    if (VRegToType.second.isSized() &&
+    if (VRegToType.second.isValid() &&
         VRegToType.second.getSizeInBits() > (RC->getSize() * 8))
       llvm_unreachable(
           "Virtual register has explicit size different from its class size");
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 808f81a567b..33bf9abc8ef 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1051,7 +1051,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
           }
 
           // Make sure the register fits into its register bank if any.
-          if (RegBank && Ty.isSized() &&
+          if (RegBank && Ty.isValid() &&
               RegBank->getSize() < Ty.getSizeInBits()) {
             report("Register bank is too small for virtual register", MO,
                    MONum);
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index e45d718c2b0..efb2dbc64a9 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -50,8 +50,8 @@ static bool unsupportedBinOp(const MachineInstr &I,
                              const MachineRegisterInfo &MRI,
                              const AArch64RegisterInfo &TRI) {
   LLT Ty = MRI.getType(I.getOperand(0).getReg());
-  if (!Ty.isSized()) {
-    DEBUG(dbgs() << "Generic binop should be sized\n");
+  if (!Ty.isValid()) {
+    DEBUG(dbgs() << "Generic binop register should be typed\n");
     return true;
   }
 
@@ -220,9 +220,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return false;
   }
 
-  const LLT Ty = I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg())
-                                         : LLT::unsized();
-  assert(Ty.isValid() && "Generic instruction doesn't have a type");
+  LLT Ty =
+      I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
 
   switch (I.getOpcode()) {
   case TargetOpcode::G_BR: {
diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index 13a2018ac58..e2165b58df5 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -149,7 +149,6 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
   }
 
   // Control-flow
-  setAction({G_BR, LLT::unsized()}, Legal);
   setAction({G_BRCOND, s32}, Legal);
   for (auto Ty : {s1, s8, s16})
     setAction({G_BRCOND, Ty}, WidenScalar);
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index ac433db6b85..d0da232bdce 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -188,7 +188,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     BankID = AArch64::GPRRegBankID;
 
   Mapping = InstructionMapping{1, 1, MI.getNumOperands()};
-  int Size = Ty.isSized() ? Ty.getSizeInBits() : 0;
+  int Size = Ty.isValid() ? Ty.getSizeInBits() : 0;
   for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
     Mapping.setOperandMapping(Idx, Size, getRegBank(BankID));