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-rw-r--r--llvm/lib/Target/ARM/ARM.td8
-rw-r--r--llvm/lib/Target/ARM/ARMAsmPrinter.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp19
-rw-r--r--llvm/lib/Target/ARM/ARMFrameLowering.cpp17
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp12
-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.cpp19
-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.h9
-rw-r--r--llvm/lib/Target/ARM/ARMTargetTransformInfo.h4
8 files changed, 68 insertions, 22 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 66bfd4c82e2..285dad1cf29 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -391,9 +391,11 @@ def FeatureExecuteOnly : SubtargetFeature<"execute-only",
"Enable the generation of "
"execute only code.">;
-def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
- "Reserve R9, making it unavailable"
- " as GPR">;
+foreach i = {6-11} in
+ def FeatureReserveR#i : SubtargetFeature<"reserve-r"#i,
+ "ReservedGPRegisters["#i#"]", "true",
+ "Reserve R"#i#", making it "
+ "unavailable as a GPR">;
def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
"Don't use movt/movw pairs for "
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index ed0969fa625..10153dd2e39 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -752,7 +752,7 @@ void ARMAsmPrinter::emitAttributes() {
if (STI.isRWPI())
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
ARMBuildAttrs::R9IsSB);
- else if (STI.isR9Reserved())
+ else if (STI.isGPRegisterReserved(9))
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
ARMBuildAttrs::R9Reserved);
else
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 4ace52b32e9..afcdb648cbc 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -198,9 +198,11 @@ getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, getFramePointerReg(STI));
if (hasBasePointer(MF))
markSuperRegs(Reserved, BasePtr);
- // Some targets reserve R9.
- if (STI.isR9Reserved())
- markSuperRegs(Reserved, ARM::R9);
+ for (size_t R = 0; R < ARM::GPRRegClass.getNumRegs(); ++R) {
+ if (STI.isGPRegisterReserved(R)) {
+ markSuperRegs(Reserved, ARM::R0 + R);
+ }
+ }
// Reserve D16-D31 if the subtarget doesn't support them.
if (!STI.hasD32()) {
static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
@@ -280,7 +282,7 @@ ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
case ARM::GPRRegClassID: {
bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
? TFI->hasFP(MF) : true;
- return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
+ return 10 - HasFP - STI.getNumGPRegistersReserved();
}
case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
case ARM::DPRRegClassID:
@@ -380,6 +382,11 @@ bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
const ARMFrameLowering *TFI = getFrameLowering(MF);
+ const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
+
+ // Disable base pointer R6 if -ffixed-r6 is used.
+ if (STI.isGPRegisterReserved(BasePtr - ARM::R0))
+ return false;
// If we have stack realignment and VLAs, we have no pointer to use to
// access the stack. If we have stack realignment, and a large call frame,
@@ -416,6 +423,7 @@ bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
const MachineRegisterInfo *MRI = &MF.getRegInfo();
const ARMFrameLowering *TFI = getFrameLowering(MF);
+ const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
// We can't realign the stack if:
// 1. Dynamic stack realignment is explicitly disabled,
// 2. There are VLAs in the function and the base pointer is disabled.
@@ -425,6 +433,9 @@ bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
// register allocation with frame pointer elimination, it is too late now.
if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
return false;
+ // Disable base pointer R6 if -ffixed-r6 is used.
+ if (STI.isGPRegisterReserved(BasePtr - ARM::R0))
+ return false;
// We may also need a base pointer if there are dynamic allocas or stack
// pointer adjustments around calls.
if (TFI->hasReservedCallFrame(MF))
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 5428bd6c94b..106894e28f0 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -1704,6 +1704,19 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
+ if (STI.isRWPI() && Reg == ARM::R9) {
+ // Paranoid check for use of R9 with RWPI. Clobbering R9 with -frwpi will
+ // emit warnings about undefined behaviour but maybe theres's a valid use
+ // case so on that basis allow it to be pushed/popped in the
+ // prologue/epilogue.
+ } else if (Reg > ARM::R0 && ARM::GPRRegClass.contains(Reg) &&
+ STI.isGPRegisterReserved(Reg - ARM::R0)) {
+ LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << " has been reserved and"
+ << " should not be allocatable"
+ << " or spillable.\n");
+ SavedRegs.reset(Reg);
+ continue;
+ }
bool Spilled = false;
if (SavedRegs.test(Reg)) {
Spilled = true;
@@ -1948,7 +1961,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
<< " is saved low register, RegDeficit = "
<< RegDeficit << "\n");
- } else {
+ } else if (!STI.isGPRegisterReserved(Reg - ARM::R0)) {
AvailableRegs.push_back(Reg);
LLVM_DEBUG(
dbgs()
@@ -1963,7 +1976,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
--RegDeficit;
LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
<< RegDeficit << "\n");
- } else {
+ } else if (!STI.isGPRegisterReserved(7)) {
AvailableRegs.push_back(ARM::R7);
LLVM_DEBUG(
dbgs()
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index c395a4feea7..b1d1d4fd5fc 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5572,9 +5572,15 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
const MachineFunction &MF) const {
Register Reg = StringSwitch<unsigned>(RegName)
- .Case("sp", ARM::SP)
- .Default(0);
- if (Reg)
+ .Case("r6", ARM::R6)
+ .Case("r7", ARM::R7)
+ .Case("r8", ARM::R8)
+ .Case("r9", ARM::R9)
+ .Case("r10", ARM::R10)
+ .Case("r11", ARM::R11)
+ .Case("sp", ARM::SP)
+ .Default(ARM::NoRegister);
+ if (Reg != ARM::NoRegister)
return Reg;
report_fatal_error(Twine("Invalid register name \""
+ StringRef(RegName) + "\"."));
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index eb4d39b01cb..7a57376a689 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -98,8 +98,9 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
const ARMBaseTargetMachine &TM, bool IsLittle,
bool MinSize)
: ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
- CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),
- TargetTriple(TT), Options(TM.Options), TM(TM),
+ ReservedGPRegisters(ARM::GPRRegClass.getNumRegs()), CPUString(CPU),
+ OptMinSize(MinSize), IsLittle(IsLittle), TargetTriple(TT),
+ Options(TM.Options), TM(TM),
FrameLowering(initializeFrameLowering(CPU, FS)),
// At this point initializeSubtargetDependencies has been called so
// we can query directly.
@@ -253,8 +254,18 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
(Options.UnsafeFPMath || isTargetDarwin()))
UseNEONForSinglePrecisionFP = true;
- if (isRWPI())
- ReserveR9 = true;
+ if (isRWPI() || (isTargetMachO() && !HasV6Ops))
+ ReservedGPRegisters.set(9);
+
+ // Throw an error when trying to reserve a target's FP register. It may
+ // be used by the compiler even when frame pointer elimination is enabled.
+ // FIXME: Throw this error if -frame-pointer=none is not set; otherwise
+ // only emit a warning.
+ const int restFP = (useR7AsFramePointer()) ? 7 : 11;
+ if (isGPRegisterReserved(restFP))
+ report_fatal_error(
+ "Register r" + std::to_string(restFP) +
+ " has been specified but is used as the frame pointer for this target.");
// If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
if (MVEVectorCostFactor == 0)
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index f582a92f656..c5836a3eca7 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -229,8 +229,8 @@ protected:
/// NoARM - True if subtarget does not support ARM mode execution.
bool NoARM = false;
- /// ReserveR9 - True if R9 is not available as a general purpose register.
- bool ReserveR9 = false;
+ // ReservedGPRegisters[i] - R#i is not available as a general purpose register
+ BitVector ReservedGPRegisters;
/// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
/// 32-bit imms (including global addresses).
@@ -763,8 +763,9 @@ public:
bool isAClass() const { return ARMProcClass == AClass; }
bool isReadTPHard() const { return ReadTPHard; }
- bool isR9Reserved() const {
- return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
+ bool isGPRegisterReserved(size_t i) const { return ReservedGPRegisters[i]; }
+ unsigned getNumGPRegistersReserved() const {
+ return ReservedGPRegisters.count();
}
bool useR7AsFramePointer() const {
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index 5bb3bcaf10e..c1fd01d2df9 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -76,7 +76,9 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
- ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,
+ ARM::FeatureExecuteOnly, ARM::FeatureReserveR6, ARM::FeatureReserveR7,
+ ARM::FeatureReserveR8, ARM::FeatureReserveR9, ARM::FeatureReserveR10,
+ ARM::FeatureReserveR11, ARM::FeatureNoMovt,
ARM::FeatureNoNegativeImmediates
};
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