diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 29 |
2 files changed, 47 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index d2a6e31e660..b3c000430d1 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -15,14 +15,26 @@ let Predicates = [HasSVE] in { defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; - defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">; + def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">; + def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">; + def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">; + def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">; defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; + defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">; + defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">; + defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">; + defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">; + defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; + defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">; + defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">; + defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">; + // Splat immediate (unpredicated) defm DUP_ZI : sve_int_dup_imm<"dup">; @@ -459,4 +471,9 @@ let Predicates = [HasSVE] in { defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">; defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">; + + + // InstAliases + def : InstAlias<"mov $Zd, $Zn", + (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>; } diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 771d83d9a17..b61ecfaa34f 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -399,6 +399,13 @@ class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc, let Constraints = "$Zdn = $_Zdn"; } +multiclass sve_int_bin_pred_log<bits<3> opc, string asm> { + def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; + def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; + def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; +} + multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> { def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; @@ -470,6 +477,28 @@ multiclass sve_int_arith_imm0<bits<3> opc, string asm> { def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; } + +//===----------------------------------------------------------------------===// +// SVE Bitwise Logical - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_int_bin_cons_log<bits<2> opc, string asm> +: I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{1-0}; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b001100; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + //===----------------------------------------------------------------------===// //SVE Index Generation Group //===----------------------------------------------------------------------===// |
