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-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp4
-rw-r--r--llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td35
-rw-r--r--llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td73
-rw-r--r--llvm/lib/Target/Mips/MicroMipsInstrFormats.td2
-rw-r--r--llvm/lib/Target/Mips/MicroMipsInstrInfo.td30
-rw-r--r--llvm/lib/Target/Mips/Mips32r6InstrInfo.td7
-rw-r--r--llvm/lib/Target/Mips/Mips64InstrInfo.td46
-rw-r--r--llvm/lib/Target/Mips/Mips64r6InstrInfo.td6
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td30
9 files changed, 173 insertions, 60 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 711e548cb08..61b53788bf3 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -81,6 +81,9 @@ static void LowerLargeShift(MCInst& Inst) {
case Mips::DSLL_MM64R6:
Inst.setOpcode(Mips::DSLL32_MM64R6);
return;
+ case Mips::DSRL_MM64R6:
+ Inst.setOpcode(Mips::DSRL32_MM64R6);
+ return;
case Mips::DSRA_MM64R6:
Inst.setOpcode(Mips::DSRA32_MM64R6);
return;
@@ -195,6 +198,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
case Mips::DSRA:
case Mips::DROTR:
case Mips::DSLL_MM64R6:
+ case Mips::DSRL_MM64R6:
case Mips::DSRA_MM64R6:
case Mips::DROTR_MM64R6:
LowerLargeShift(TmpInst);
diff --git a/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td b/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td
index ead89c42873..4add305522f 100644
--- a/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td
@@ -173,6 +173,37 @@ class POOL32S_2RSA5B0_FM_MMR6<string instr_asm, bits<9> funct>
let Inst{8-0} = funct;
}
+class LD_SD_32_2R_OFFSET16_FM_MMR6<string instr_asm, bits<6> op>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> rt;
+ bits<21> addr;
+ bits<5> base = addr{20-16};
+ bits<16> offset = addr{15-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = op;
+ let Inst{25-21} = rt;
+ let Inst{20-16} = base;
+ let Inst{15-0} = offset;
+}
+
+class POOL32C_2R_OFFSET12_FM_MMR6<string instr_asm, bits<4> funct>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> rt;
+ bits<21> addr;
+ bits<5> base = addr{20-16};
+ bits<12> offset = addr{11-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b011000;
+ let Inst{25-21} = rt;
+ let Inst{20-16} = base;
+ let Inst{15-12} = funct;
+ let Inst{11-0} = offset;
+}
+
class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> rt;
@@ -185,6 +216,6 @@ class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct>
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-11} = rd;
- let Inst{10-9} = 0b00;
- let Inst{8-0} = funct;
+ let Inst{10-9} = 0b00;
+ let Inst{8-0} = funct;
}
diff --git a/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td
index 1ebee40d4df..87c41deb85a 100644
--- a/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td
@@ -60,6 +60,13 @@ class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
+class LD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"ld", 0b110111>;
+class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
+class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
+class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>;
+class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>;
+class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
+class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
//===----------------------------------------------------------------------===//
//
@@ -221,8 +228,9 @@ class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
dag OutOperandList = (outs GPR64Opnd:$rt);
dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
- InstrItinClass Itinerary = itin;
list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
+ InstrItinClass Itinerary = itin;
+ Format Form = FrmR;
string TwoOperandAliasConstraint = "$rs = $rt";
string BaseOpcode = instr_asm;
}
@@ -252,6 +260,53 @@ class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
II_DROTR32>;
class DROTRV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"drotrv", II_DROTRV, rotr>;
+class DSRL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl", uimm6, II_DSRL, srl,
+ immZExt6>;
+class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5, II_DSRL32>;
+class DSRLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrlv", II_DSRLV, srl>;
+
+class Load_MM64R6<string instr_asm, Operand MemOpnd, InstrItinClass itin,
+ SDPatternOperator OpNode = null_frag> {
+ dag OutOperandList = (outs GPR64Opnd:$rt);
+ dag InOperandList = (ins MemOpnd:$addr);
+ string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
+ list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode addr:$addr))];
+ InstrItinClass Itinerary = itin;
+ Format Form = FrmI;
+ bit mayLoad = 1;
+ bit canFoldAsLoad = 1;
+ string BaseOpcode = instr_asm;
+}
+
+class LD_MM64R6_DESC : Load_MM64R6<"ld", mem_simm16, II_LD, load> {
+ string DecoderMethod = "DecodeMemMMImm16";
+}
+class LWU_MM64R6_DESC : Load_MM64R6<"lwu", mem_simm12, II_LWU, zextloadi32>{
+ string DecoderMethod = "DecodeMemMMImm12";
+}
+
+class LLD_MM64R6_DESC {
+ dag OutOperandList = (outs GPR64Opnd:$rt);
+ dag InOperandList = (ins mem_simm12:$addr);
+ string AsmString = "lld\t$rt, $addr";
+ list<dag> Pattern = [];
+ bit mayLoad = 1;
+ InstrItinClass Itinerary = II_LLD;
+ string BaseOpcode = "lld";
+ string DecoderMethod = "DecodeMemMMImm12";
+}
+
+class SD_MM64R6_DESC {
+ dag OutOperandList = (outs);
+ dag InOperandList = (ins GPR64Opnd:$rt, mem_simm16:$addr);
+ string AsmString = "sd\t$rt, $addr";
+ list<dag> Pattern = [(store GPR64Opnd:$rt, addr:$addr)];
+ InstrItinClass Itinerary = II_SD;
+ Format Form = FrmI;
+ bit mayStore = 1;
+ string BaseOpcode = "sd";
+ string DecoderMethod = "DecodeMemMMImm16";
+}
//===----------------------------------------------------------------------===//
//
@@ -343,6 +398,20 @@ let DecoderNamespace = "MicroMipsR6" in {
ISA_MICROMIPS64R6;
def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_ENC, DROTRV_MM64R6_DESC,
ISA_MICROMIPS64R6;
+ def LD_MM64R6 : StdMMR6Rel, LD_MM64R6_ENC, LD_MM64R6_DESC,
+ ISA_MICROMIPS64R6;
+ def LLD_MM64R6 : StdMMR6Rel, R6MMR6Rel, LLD_MM64R6_ENC, LLD_MM64R6_DESC,
+ ISA_MICROMIPS64R6;
+ def LWU_MM64R6 : StdMMR6Rel, LWU_MM64R6_ENC, LWU_MM64R6_DESC,
+ ISA_MICROMIPS64R6;
+ def SD_MM64R6 : StdMMR6Rel, SD_MM64R6_ENC, SD_MM64R6_DESC,
+ ISA_MICROMIPS64R6;
+ def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
+ ISA_MICROMIPS64R6;
+ def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
+ ISA_MICROMIPS64R6;
+ def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
+ ISA_MICROMIPS64R6;
}
//===----------------------------------------------------------------------===//
@@ -397,6 +466,8 @@ def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
(DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
+def : MipsPat<(atomic_load_64 addr:$a), (LD_MM64R6 addr:$a)>, ISA_MICROMIPS64R6;
+
//===----------------------------------------------------------------------===//
//
// Instruction aliases
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
index 126c3bf23f8..79ef6482180 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -675,7 +675,7 @@ class TEQI_FM_MM<bits<5> funct> : MMArch {
let Inst{15-0} = imm16;
}
-class LL_FM_MM<bits<4> funct> {
+class LL_FM_MM<bits<4> funct> : MMArch {
bits<5> rt;
bits<21> addr;
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index 376b3739571..00ca54a8cc1 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -1,10 +1,6 @@
def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
-def simm12 : Operand<i32> {
- let DecoderMethod = "DecodeSimm12";
-}
-
def simm9_addiusp : Operand<i32> {
let EncoderMethod = "getSImm9AddiuspValue";
let DecoderMethod = "DecodeSimm9SP";
@@ -142,21 +138,6 @@ def mem_mm_4sp : Operand<i32> {
let OperandType = "OPERAND_MEMORY";
}
-def MipsMemSimm12AsmOperand : AsmOperandClass {
- let Name = "MemOffsetSimm12";
- let SuperClasses = [MipsMemAsmOperand];
- let RenderMethod = "addMemOperands";
- let ParserMethod = "parseMemOperand";
- let PredicateMethod = "isMemWithSimmOffset<12>";
- let DiagnosticType = "MemSImm12";
-}
-
-def mem_simm12 : mem_generic {
- let MIOperandInfo = (ops ptr_rc, simm12);
- let EncoderMethod = "getMemEncoding";
- let ParserMatchClass = MipsMemSimm12AsmOperand;
-}
-
def jmptarget_mm : Operand<OtherVT> {
let EncoderMethod = "getJumpTargetOpValueMM";
}
@@ -304,10 +285,10 @@ class SCEBaseMM<string opstr, RegisterOperand RO> :
}
class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary> :
- InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
+ InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :
+ InstSE<(outs RO:$rt), (ins MO:$addr),
!strconcat(opstr, "\t$rt, $addr"),
- [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
+ [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMemMMImm12";
let canFoldAsLoad = 1;
let mayLoad = 1;
@@ -790,8 +771,6 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
- def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
-
/// Load and Store Instructions - unaligned
def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x0>;
@@ -983,6 +962,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
let DecoderNamespace = "MicroMips" in {
def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
+ mem_simm12>, LL_FM_MM<0xe>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 9e108efe5bf..cee169e6c5e 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -677,16 +677,17 @@ class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> {
+ Operand MemOpnd, InstrItinClass itin>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
- dag InOperandList = (ins mem_simm9:$addr);
+ dag InOperandList = (ins MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayLoad = 1;
InstrItinClass Itinerary = itin;
}
-class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, II_LL>;
+class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
InstrItinClass itin> {
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index 21e34d83e83..88cfec5bc13 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -140,30 +140,24 @@ let AdditionalPredicates = [NotInMicroMips] in {
def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
shl, immZExt6>,
SRA_FM<0x38, 0>, ISA_MIPS3;
-}
-def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
+ def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
+ srl, immZExt6>,
SRA_FM<0x3a, 0>, ISA_MIPS3;
-let AdditionalPredicates = [NotInMicroMips] in {
def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
sra, immZExt6>,
SRA_FM<0x3b, 0>, ISA_MIPS3;
def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
SRLV_FM<0x14, 0>, ISA_MIPS3;
-}
-def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
- SRLV_FM<0x16, 0>, ISA_MIPS3;
-let AdditionalPredicates = [NotInMicroMips] in {
def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
SRLV_FM<0x17, 0>, ISA_MIPS3;
-}
-let AdditionalPredicates = [NotInMicroMips] in {
+ def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
+ SRLV_FM<0x16, 0>, ISA_MIPS3;
def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
II_DSLL32>,
SRA_FM<0x3c, 0>, ISA_MIPS3;
-}
-def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
- SRA_FM<0x3e, 0>, ISA_MIPS3;
-let AdditionalPredicates = [NotInMicroMips] in {
+ def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd,
+ II_DSRL32>,
+ SRA_FM<0x3e, 0>, ISA_MIPS3;
def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
II_DSRA32>,
SRA_FM<0x3f, 0>, ISA_MIPS3;
@@ -193,9 +187,16 @@ def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
}
-def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
-def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
-def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
+ LW_FM<0x27>, ISA_MIPS3;
+ def LD : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
+ LW_FM<0x37>, ISA_MIPS3;
+ def SD : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
+ LW_FM<0x3f>, ISA_MIPS3;
+}
+
+
/// load/store left/right
let isCodeGenOnly = 1 in {
@@ -215,7 +216,10 @@ def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
ISA_MIPS3_NOT_32R6_64R6;
/// Load-linked, Store-conditional
-def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
+ ISA_MIPS3_NOT_32R6_64R6;
+}
def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips],
@@ -687,12 +691,12 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dsra $rd, $rt, $rs",
(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
-def : MipsInstAlias<"dsrl $rd, $rt, $rs",
- (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
- ISA_MIPS3;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<"dsrl $rd, $rt, $rs",
+ (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
+ ISA_MIPS3;
// Two operand (implicit 0 selector) versions:
-let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dmtc0 $rt, $rd",
(DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
def : MipsInstAlias<"dmfc0 $rt, $rd",
diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
index 2722728cbba..64effbef8a6 100644
--- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -71,7 +71,7 @@ class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
-class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, II_LLD>;
+class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm16, II_LLD>;
class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
@@ -88,7 +88,7 @@ class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
list<Register> Defs = [AT];
}
-class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, II_LL>;
+class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
//===----------------------------------------------------------------------===//
//
@@ -117,9 +117,9 @@ let AdditionalPredicates = [NotInMicroMips] in {
def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
+ def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
}
def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
-def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
let DecoderNamespace = "Mips32r6_64r6_GP64" in {
def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 925dd881e0e..cdd61fd0e2b 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -880,6 +880,15 @@ def MipsMemSimm10AsmOperand : AsmOperandClass {
let DiagnosticType = "MemSImm10";
}
+def MipsMemSimm12AsmOperand : AsmOperandClass {
+ let Name = "MemOffsetSimm12";
+ let SuperClasses = [MipsMemAsmOperand];
+ let RenderMethod = "addMemOperands";
+ let ParserMethod = "parseMemOperand";
+ let PredicateMethod = "isMemWithSimmOffset<12>";
+ let DiagnosticType = "MemSImm12";
+}
+
foreach I = {1, 2, 3} in
def MipsMemSimm10Lsl # I # AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm10_" # I;
@@ -939,6 +948,10 @@ def mem_msa : mem_generic {
let EncoderMethod = "getMSAMemEncoding";
}
+def simm12 : Operand<i32> {
+ let DecoderMethod = "DecodeSimm12";
+}
+
def mem_simm9 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm9);
let EncoderMethod = "getMemEncoding";
@@ -965,6 +978,12 @@ def mem_simm11 : mem_generic {
let ParserMatchClass = MipsMemSimm11AsmOperand;
}
+def mem_simm12 : mem_generic {
+ let MIOperandInfo = (ops ptr_rc, simm12);
+ let EncoderMethod = "getMemEncoding";
+ let ParserMatchClass = MipsMemSimm12AsmOperand;
+}
+
def mem_simm16 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding";
@@ -1167,8 +1186,9 @@ class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
}
class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
- StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
+ InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr,
+ DAGOperand MO = mem> :
+ StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
// Load/Store Left/Right
let canFoldAsLoad = 1 in
@@ -1540,9 +1560,9 @@ class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
[(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
-class LLBase<string opstr, RegisterOperand RO> :
- InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [], II_LL, FrmI> {
+class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> :
+ InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
+ [], II_LL, FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let mayLoad = 1;
}
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