diff options
Diffstat (limited to 'llvm/lib')
6 files changed, 141 insertions, 17 deletions
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp index 2d92b93ca70..0d591c04535 100644 --- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp +++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp @@ -46,7 +46,9 @@ static unsigned MVTToWasmReg(MVT::SimpleValueType Type) { case MVT::v16i8: return WebAssembly::V128_0; case MVT::v8i16: return WebAssembly::V128_0; case MVT::v4i32: return WebAssembly::V128_0; + case MVT::v2i64: return WebAssembly::V128_0; case MVT::v4f32: return WebAssembly::V128_0; + case MVT::v2f64: return WebAssembly::V128_0; default: return MVT::INVALID_SIMPLE_VALUE_TYPE; } } @@ -194,6 +196,7 @@ public: const MCInstrInfo &mii, const MCTargetOptions &Options) : MCTargetAsmParser(Options, sti, mii), Parser(Parser), Lexer(Parser.getLexer()), LastLabel(nullptr) { + setAvailableFeatures(ComputeAvailableFeatures(sti.getFeatureBits())); } #define GET_ASSEMBLER_HEADER @@ -232,7 +235,13 @@ public: .Case("i8x16", MVT::v16i8) .Case("i16x8", MVT::v8i16) .Case("i32x4", MVT::v4i32) + .Case("i64x2", MVT::v2i64) .Case("f32x4", MVT::v4f32) + .Case("f64x2", MVT::v2f64) + // arbitrarily chosen vector type to associate with "v128" + // FIXME: should these be EVTs to avoid this arbitrary hack? Do we want + // to accept more specific SIMD register types? + .Case("v128", MVT::v16i8) .Default(MVT::INVALID_SIMPLE_VALUE_TYPE); } diff --git a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp index 2f0960271e3..9f6797da3a2 100644 --- a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp +++ b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp @@ -92,14 +92,18 @@ static bool parseLEBImmediate(MCInst &MI, uint64_t &Size, } template <typename T> -bool parseFPImmediate(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes) { +bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes) { if (Size + sizeof(T) > Bytes.size()) return false; T Val; memcpy(&Val, Bytes.data() + Size, sizeof(T)); support::endian::byte_swap<T, support::endianness::little>(Val); Size += sizeof(T); - MI.addOperand(MCOperand::createFPImm(static_cast<double>(Val))); + if (std::is_floating_point<T>::value) { + MI.addOperand(MCOperand::createFPImm(static_cast<double>(Val))); + } else { + MI.addOperand(MCOperand::createImm(static_cast<int64_t>(Val))); + } return true; } @@ -160,12 +164,33 @@ MCDisassembler::DecodeStatus WebAssemblyDisassembler::getInstruction( } // FP operands. case WebAssembly::OPERAND_F32IMM: { - if (!parseFPImmediate<float>(MI, Size, Bytes)) + if (!parseImmediate<float>(MI, Size, Bytes)) return MCDisassembler::Fail; break; } case WebAssembly::OPERAND_F64IMM: { - if (!parseFPImmediate<double>(MI, Size, Bytes)) + if (!parseImmediate<double>(MI, Size, Bytes)) + return MCDisassembler::Fail; + break; + } + // Vector lane operands (not LEB encoded). + case WebAssembly::OPERAND_VEC_I8IMM: { + if (!parseImmediate<uint8_t>(MI, Size, Bytes)) + return MCDisassembler::Fail; + break; + } + case WebAssembly::OPERAND_VEC_I16IMM: { + if (!parseImmediate<uint16_t>(MI, Size, Bytes)) + return MCDisassembler::Fail; + break; + } + case WebAssembly::OPERAND_VEC_I32IMM: { + if (!parseImmediate<uint32_t>(MI, Size, Bytes)) + return MCDisassembler::Fail; + break; + } + case WebAssembly::OPERAND_VEC_I64IMM: { + if (!parseImmediate<uint64_t>(MI, Size, Bytes)) return MCDisassembler::Fail; break; } diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp index 417912604e0..bff074d987c 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp @@ -90,17 +90,34 @@ void WebAssemblyMCCodeEmitter::encodeInstruction( const MCOperandInfo &Info = Desc.OpInfo[i]; LLVM_DEBUG(dbgs() << "Encoding immediate: type=" << int(Info.OperandType) << "\n"); - if (Info.OperandType == WebAssembly::OPERAND_I32IMM) { + switch (Info.OperandType) { + case WebAssembly::OPERAND_I32IMM: encodeSLEB128(int32_t(MO.getImm()), OS); - } else if (Info.OperandType == WebAssembly::OPERAND_OFFSET32) { + break; + case WebAssembly::OPERAND_OFFSET32: encodeULEB128(uint32_t(MO.getImm()), OS); - } else if (Info.OperandType == WebAssembly::OPERAND_I64IMM) { + break; + case WebAssembly::OPERAND_I64IMM: encodeSLEB128(int64_t(MO.getImm()), OS); - } else if (Info.OperandType == WebAssembly::OPERAND_GLOBAL) { - llvm_unreachable("wasm globals should only be accessed symbolicly"); - } else if (Info.OperandType == WebAssembly::OPERAND_SIGNATURE) { + break; + case WebAssembly::OPERAND_SIGNATURE: OS << uint8_t(MO.getImm()); - } else { + break; + case WebAssembly::OPERAND_VEC_I8IMM: + support::endian::write<uint8_t>(OS, MO.getImm(), support::little); + break; + case WebAssembly::OPERAND_VEC_I16IMM: + support::endian::write<uint16_t>(OS, MO.getImm(), support::little); + break; + case WebAssembly::OPERAND_VEC_I32IMM: + support::endian::write<uint32_t>(OS, MO.getImm(), support::little); + break; + case WebAssembly::OPERAND_VEC_I64IMM: + support::endian::write<uint64_t>(OS, MO.getImm(), support::little); + break; + case WebAssembly::OPERAND_GLOBAL: + llvm_unreachable("wasm globals should only be accessed symbolicly"); + default: encodeULEB128(uint64_t(MO.getImm()), OS); } } else { diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h index b4639b4afdc..4ca921481dc 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h @@ -59,6 +59,14 @@ enum OperandType { OPERAND_F32IMM, /// 64-bit floating-point immediates. OPERAND_F64IMM, + /// 8-bit vector lane immediate + OPERAND_VEC_I8IMM, + /// 16-bit vector lane immediate + OPERAND_VEC_I16IMM, + /// 32-bit vector lane immediate + OPERAND_VEC_I32IMM, + /// 64-bit vector lane immediate + OPERAND_VEC_I64IMM, /// 32-bit unsigned function indices. OPERAND_FUNCTION32, /// 32-bit unsigned memory offsets. diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td index 3f97ef5f7b7..d9e87e017a6 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -118,6 +118,18 @@ def f32imm_op : Operand<f32>; let OperandType = "OPERAND_F64IMM" in def f64imm_op : Operand<f64>; +let OperandType = "OPERAND_VEC_I8IMM" in +def vec_i8imm_op : Operand<i32>; + +let OperandType = "OPERAND_VEC_I16IMM" in +def vec_i16imm_op : Operand<i32>; + +let OperandType = "OPERAND_VEC_I32IMM" in +def vec_i32imm_op : Operand<i32>; + +let OperandType = "OPERAND_VEC_I64IMM" in +def vec_i64imm_op : Operand<i64>; + let OperandType = "OPERAND_FUNCTION32" in def function32_op : Operand<i32>; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 2a4505173fb..08b925aeee9 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -12,18 +12,71 @@ /// //===----------------------------------------------------------------------===// -// immediate argument types -def ImmByte : ImmLeaf<i32, [{ return 0 <= Imm && Imm < 256; }]>; +// constrained immediate argument types +foreach SIZE = [8, 16] in +def ImmI#SIZE : ImmLeaf<i32, "return (Imm & ((1UL << "#SIZE#") - 1)) == Imm;">; foreach SIZE = [2, 4, 8, 16, 32] in def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; +// const vectors +multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { + defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, + [(set V128:$dst, (vec_t pat))], + "v128.const\t$dst, "#args, + "v128.const\t"#args, 0>; +} +defm "" : ConstVec<v16i8, + (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1, + vec_i8imm_op:$i2, vec_i8imm_op:$i3, + vec_i8imm_op:$i4, vec_i8imm_op:$i5, + vec_i8imm_op:$i6, vec_i8imm_op:$i7, + vec_i8imm_op:$i8, vec_i8imm_op:$i9, + vec_i8imm_op:$iA, vec_i8imm_op:$iB, + vec_i8imm_op:$iC, vec_i8imm_op:$iD, + vec_i8imm_op:$iE, vec_i8imm_op:$iF), + (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3, + ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7, + ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB, + ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF), + !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ", + "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>; +defm "" : ConstVec<v8i16, + (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1, + vec_i16imm_op:$i2, vec_i16imm_op:$i3, + vec_i16imm_op:$i4, vec_i16imm_op:$i5, + vec_i16imm_op:$i6, vec_i16imm_op:$i7), + (build_vector + ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3, + ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7), + "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">; +defm "" : ConstVec<v4i32, + (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1, + vec_i32imm_op:$i2, vec_i32imm_op:$i3), + (build_vector (i32 imm:$i0), (i32 imm:$i1), + (i32 imm:$i2), (i32 imm:$i3)), + "$i0, $i1, $i2, $i3">; +defm "" : ConstVec<v2i64, + (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1), + (build_vector (i64 imm:$i0), (i64 imm:$i1)), + "$i0, $i1">; +defm "" : ConstVec<v4f32, + (ins f32imm_op:$i0, f32imm_op:$i1, + f32imm_op:$i2, f32imm_op:$i3), + (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1), + (f32 fpimm:$i2), (f32 fpimm:$i3)), + "$i0, $i1, $i2, $i3">; +defm "" : ConstVec<v2f64, + (ins f64imm_op:$i0, f64imm_op:$i1), + (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), + "$i0, $i1">; + // lane extraction multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t, WebAssemblyRegClass reg_t, bits<32> simdop, string suffix = "", SDNode extract = vector_extract> { defm EXTRACT_LANE_#vec_t#suffix : - SIMD_I<(outs reg_t:$dst), (ins V128:$vec, I32:$idx), - (outs), (ins I32:$idx), + SIMD_I<(outs reg_t:$dst), (ins V128:$vec, i32imm_op:$idx), + (outs), (ins i32imm_op:$idx), [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))], vec#".extract_lane"#suffix#"\t$dst, $vec, $idx", vec#".extract_lane"#suffix#"\t$idx", simdop>; @@ -73,8 +126,8 @@ def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))), multiclass ReplaceLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t, ValueType lane_t, ImmLeaf imm_t, bits<32> simdop> { defm REPLACE_LANE_#vec_t : - SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$idx, reg_t:$x), - (outs), (ins I32:$idx), + SIMD_I<(outs V128:$dst), (ins V128:$vec, i32imm_op:$idx, reg_t:$x), + (outs), (ins i32imm_op:$idx), [(set V128:$dst, (vector_insert (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))], vec#".replace_lane\t$dst, $vec, $idx, $x", |
