diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 7 |
2 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 2c3587e6d1a..7b551c40408 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -330,6 +330,10 @@ def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", "DisablePostRAScheduler", "true", "Don't schedule again after register allocation">; +// Enable use of alias analysis during code generation +def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", + "Use alias analysis during codegen">; + //===----------------------------------------------------------------------===// // ARM architecture class // @@ -1006,7 +1010,8 @@ def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, FeatureUseMISched, - FeatureFPAO]>; + FeatureFPAO, + FeatureUseAA]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index e23a5fe1e06..f72b97fc0d7 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -198,6 +198,9 @@ protected: /// register allocation. bool DisablePostRAScheduler = false; + /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc) + bool UseAA = false; + /// HasThumb2 - True if Thumb2 instructions are supported. bool HasThumb2 = false; @@ -723,6 +726,10 @@ public: /// True for some subtargets at > -O0. bool enablePostRAScheduler() const override; + /// Enable use of alias analysis during code generation (during MI + /// scheduling, DAGCombine, etc.). + bool useAA() const override { return UseAA; } + // enableAtomicExpand- True if we need to expand our atomics. bool enableAtomicExpand() const override; |
