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-rw-r--r--llvm/lib/Target/X86/X86ScheduleBtVer2.td16
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index b07258bf75e..8811a5dfe5f 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -206,6 +206,22 @@ def JWriteIDiv32Ld : SchedWriteRes<[JLAGU, JALU1, JDiv]> {
def : InstRW<[JWriteIDiv32], (instrs DIV32r, IDIV32r)>;
def : InstRW<[JWriteIDiv32Ld], (instrs DIV32m, IDIV32m)>;
+def JWriteCRC32 : SchedWriteRes<[JALU01]> {
+ let Latency = 3;
+ let ResourceCycles = [4];
+ let NumMicroOps = 3;
+}
+def : InstRW<[JWriteCRC32], (instrs CRC32r32r8, CRC32r32r16, CRC32r32r32,
+ CRC32r64r8, CRC32r64r64)>;
+
+def JWriteCRC32Ld : SchedWriteRes<[JLAGU, JALU01]> {
+ let Latency = 6;
+ let ResourceCycles = [1, 4];
+ let NumMicroOps = 3;
+}
+def : InstRW<[JWriteCRC32Ld], (instrs CRC32r32m8, CRC32r32m16, CRC32r32m32,
+ CRC32r64m8, CRC32r64m64)>;
+
////////////////////////////////////////////////////////////////////////////////
// Integer shifts and rotates.
////////////////////////////////////////////////////////////////////////////////
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