diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 21 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 18 |
2 files changed, 15 insertions, 24 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index d9364ed9050..4fbc4aa65ff 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -587,14 +587,23 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { - EVT SVT = getSetCCResultType(N->getOperand(0).getValueType()); - + EVT InVT = N->getOperand(0).getValueType(); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); - // Only use the result of getSetCCResultType if it is legal, - // otherwise just use the promoted result type (NVT). - if (!TLI.isTypeLegal(SVT)) - SVT = NVT; + EVT SVT = getSetCCResultType(InVT); + + // If we got back a type that needs to be promoted, this likely means the + // the input type also needs to be promoted. So get the promoted type for + // the input and try the query again. + if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) { + if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) { + InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); + SVT = getSetCCResultType(InVT); + } else { + // Input type isn't promoted, just use the default promoted type. + SVT = NVT; + } + } SDLoc dl(N); assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() && diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fb871266546..e258e65f165 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18214,24 +18214,6 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, if (VTOp0 == MVT::v2i32) return SDValue(); - if (VT.is128BitVector() && VTOp0.is256BitVector()) { - // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type - // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the - // legalizer firstly checks if the first operand in input to the setcc has - // a legal type. If so, then it promotes the return type to that same type. - // Otherwise, the return type is promoted to the 'next legal type' which, - // for a vector of MVT::i1 is always a 128-bit integer vector type. - // - // We reach this code only if the following two conditions are met: - // 1. Both return type and operand type have been promoted to wider types - // by the type legalizer. - // 2. The original operand type has been promoted to a 256-bit vector. - // - // Note that condition 2. only applies for AVX targets. - SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, Cond); - return DAG.getZExtOrTrunc(NewOp, dl, VT); - } - // The non-AVX512 code below works under the assumption that source and // destination types are the same. assert((Subtarget.hasAVX512() || (VT == VTOp0)) && |
