summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp4
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp6
-rw-r--r--llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp4
-rw-r--r--llvm/lib/Target/IA64/IA64AsmPrinter.cpp4
-rw-r--r--llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp2
-rw-r--r--llvm/lib/Target/Sparc/SparcAsmPrinter.cpp10
-rwxr-xr-xllvm/lib/Target/X86/X86ATTAsmPrinter.cpp2
-rwxr-xr-xllvm/lib/Target/X86/X86IntelAsmPrinter.cpp2
-rwxr-xr-xllvm/lib/Target/X86/X86IntelAsmPrinter.h2
9 files changed, 18 insertions, 18 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index b1fb52a13a5..f2a604cf6d0 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -138,7 +138,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
if (TM) MRI = TM->getRegisterInfo();
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_Register:
OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_Immediate:
@@ -235,7 +235,7 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_Register:
OutputReg(OS, MO.getReg());
break;
case MachineOperand::MO_Immediate:
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 2b7b877cb17..cf1227964a5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -104,7 +104,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
}
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op)) {
- MI->addZeroExtImm64Operand(C->getValue());
+ MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), MachineOperand::Use);
@@ -303,7 +303,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
unsigned NumVals = Flags >> 3;
- MI->addZeroExtImm64Operand(Flags);
+ MI->addImmOperand(Flags);
++i; // Skip the ID value.
switch (Flags & 7) {
@@ -323,7 +323,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
case 3: { // Immediate.
assert(NumVals == 1 && "Unknown immediate value!");
uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
- MI->addZeroExtImm64Operand(Val);
+ MI->addImmOperand(Val);
++i;
break;
}
diff --git a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
index e51b78457bb..59a85053767 100644
--- a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -77,7 +77,7 @@ FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
{
const MachineOperand &MO = MI->getOperand(opNum);
- if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+ if (MO.getType() == MachineOperand::MO_Register) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@@ -93,7 +93,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
int new_symbol;
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_Register:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
index 86b8432a3f4..13c2dfbec52 100644
--- a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -66,7 +66,7 @@ namespace {
// This method is used by the tablegen'erated instruction printer.
void printOperand(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+ if (MO.getType() == MachineOperand::MO_Register) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
//XXX Bug Workaround: See note in Printer::doInitialization about %.
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
@@ -173,7 +173,7 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
bool isBRCALLinsn /* = false */) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_Register:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 5e30fe073cb..dbd3b03e7bc 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -86,7 +86,7 @@ namespace {
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+ if (MO.isRegister()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
index d95ca9c1f97..47ed6fcda78 100644
--- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -146,7 +146,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
CloseParen = true;
}
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_Register:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
else
@@ -188,16 +188,16 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
- if (OpTy == MachineOperand::MO_VirtualRegister &&
+ if (MI->getOperand(opNum+1).isRegister() &&
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
- if (OpTy == MachineOperand::MO_Immediate &&
+ if (MI->getOperand(opNum+1).isImmediate() &&
MI->getOperand(opNum+1).getImmedValue() == 0)
return; // don't print "+0"
O << "+";
- if (OpTy == MachineOperand::MO_GlobalAddress ||
- OpTy == MachineOperand::MO_ConstantPoolIndex) {
+ if (MI->getOperand(opNum+1).isGlobalAddress() ||
+ MI->getOperand(opNum+1).isConstantPoolIndex()) {
O << "%lo(";
printOperand(MI, opNum+1);
O << ")";
diff --git a/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp b/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
index 122b012453d..92e22945b7a 100755
--- a/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -108,7 +108,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const MachineOperand &MO = MI->getOperand(OpNo);
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_Register:
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
O << '%';
diff --git a/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp b/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
index 07dab8a478c..af58df1e956 100755
--- a/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -100,7 +100,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
+ case MachineOperand::MO_Register:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << RI.get(MO.getReg()).Name;
else
diff --git a/llvm/lib/Target/X86/X86IntelAsmPrinter.h b/llvm/lib/Target/X86/X86IntelAsmPrinter.h
index 28ccfc9ed09..c594e462551 100755
--- a/llvm/lib/Target/X86/X86IntelAsmPrinter.h
+++ b/llvm/lib/Target/X86/X86IntelAsmPrinter.h
@@ -37,7 +37,7 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
void printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier = 0) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+ if (MO.isRegister()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else {
OpenPOWER on IntegriCloud