diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Support/APInt.cpp | 21 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h | 21 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h | 21 |
3 files changed, 39 insertions, 24 deletions
diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index f2f5cca946f..f3c2ca5dab9 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -19,7 +19,6 @@ #include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/bit.h" #include "llvm/Config/llvm-config.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -713,20 +712,24 @@ APInt llvm::APIntOps::GreatestCommonDivisor(APInt A, APInt B) { } APInt llvm::APIntOps::RoundDoubleToAPInt(double Double, unsigned width) { - uint64_t I = bit_cast<uint64_t>(Double); + union { + double D; + uint64_t I; + } T; + T.D = Double; // Get the sign bit from the highest order bit - bool isNeg = I >> 63; + bool isNeg = T.I >> 63; // Get the 11-bit exponent and adjust for the 1023 bit bias - int64_t exp = ((I >> 52) & 0x7ff) - 1023; + int64_t exp = ((T.I >> 52) & 0x7ff) - 1023; // If the exponent is negative, the value is < 0 so just return 0. if (exp < 0) return APInt(width, 0u); // Extract the mantissa by clearing the top 12 bits (sign + exponent). - uint64_t mantissa = (I & (~0ULL >> 12)) | 1ULL << 52; + uint64_t mantissa = (T.I & (~0ULL >> 12)) | 1ULL << 52; // If the exponent doesn't shift all bits out of the mantissa if (exp < 52) @@ -803,8 +806,12 @@ double APInt::roundToDouble(bool isSigned) const { // The leading bit of mantissa is implicit, so get rid of it. uint64_t sign = isNeg ? (1ULL << (APINT_BITS_PER_WORD - 1)) : 0; - uint64_t I = sign | (exp << 52) | mantissa; - return bit_cast<double>(I); + union { + double D; + uint64_t I; + } T; + T.I = sign | (exp << 52) | mantissa; + return T.D; } // Truncate to new width. diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h index 34b732a1ff4..62644ab2f45 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h @@ -16,7 +16,6 @@ #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" -#include "llvm/ADT/bit.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include <cassert> @@ -343,23 +342,27 @@ static inline bool isValidDecodeLogicalImmediate(uint64_t val, // static inline float getFPImmFloat(unsigned Imm) { // We expect an 8-bit binary encoding of a floating-point number here. + union { + uint32_t I; + float F; + } FPUnion; uint8_t Sign = (Imm >> 7) & 0x1; uint8_t Exp = (Imm >> 4) & 0x7; uint8_t Mantissa = Imm & 0xf; - // 8-bit FP IEEE Float Encoding + // 8-bit FP iEEEE Float Encoding // abcd efgh aBbbbbbc defgh000 00000000 00000000 // // where B = NOT(b); - uint32_t I = 0; - I |= Sign << 31; - I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; - I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; - I |= (Exp & 0x3) << 23; - I |= Mantissa << 19; - return bit_cast<float>(I); + FPUnion.I = 0; + FPUnion.I |= Sign << 31; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + FPUnion.I |= (Exp & 0x3) << 23; + FPUnion.I |= Mantissa << 19; + return FPUnion.F; } /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h index e450d3f5d75..f472b215431 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h @@ -627,22 +627,27 @@ namespace ARM_AM { // inline float getFPImmFloat(unsigned Imm) { // We expect an 8-bit binary encoding of a floating-point number here. + union { + uint32_t I; + float F; + } FPUnion; uint8_t Sign = (Imm >> 7) & 0x1; uint8_t Exp = (Imm >> 4) & 0x7; uint8_t Mantissa = Imm & 0xf; - // 8-bit FP IEEE Float Encoding + // 8-bit FP iEEEE Float Encoding // abcd efgh aBbbbbbc defgh000 00000000 00000000 // // where B = NOT(b); - uint32_t I = 0; - I |= Sign << 31; - I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; - I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; - I |= (Exp & 0x3) << 23; - I |= Mantissa << 19; - return bit_cast<float>(F); + + FPUnion.I = 0; + FPUnion.I |= Sign << 31; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + FPUnion.I |= (Exp & 0x3) << 23; + FPUnion.I |= Mantissa << 19; + return FPUnion.F; } /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit |
