2 files changed, 38 insertions, 20 deletions

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 1cfc9af9d9e..a5983479a6d 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -123,7 +123,7 @@ namespace {
 #include "X86GenDAGISel.inc"
 
   private:
-    void Select(SDOperand &Result, SDOperand N);
+    SDNode *Select(SDOperand &Result, SDOperand N);
 
     bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
     bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
@@ -646,7 +646,7 @@ static SDNode *FindCallStartFromCall(SDNode *Node) {
   return FindCallStartFromCall(Node->getOperand(0).Val);
 }
 
-void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
+SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
   SDNode *Node = N.Val;
   MVT::ValueType NVT = Node->getValueType(0);
   unsigned Opc, MOpc;
@@ -669,15 +669,14 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
     DEBUG(std::cerr << "\n");
     Indent -= 2;
 #endif
-    return;   // Already selected.
+    return NULL;   // Already selected.
   }
 
   switch (Opcode) {
     default: break;
     case X86ISD::GlobalBaseReg: 
       Result = getGlobalBaseReg();
-      ReplaceUses(N, Result);
-      return;
+      return Result.Val;
 
     case ISD::ADD: {
       // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
@@ -705,12 +704,12 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
         if (C.Val) {
           if (N.Val->hasOneUse()) {
             Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
+	    return NULL;
           } else {
             SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
             Result = SDOperand(ResNode, 0);
-            ReplaceUses(N, Result);
+	    return ResNode;
           }
-          return;
         }
       }
 
@@ -798,7 +797,7 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
       DEBUG(std::cerr << "\n");
       Indent -= 2;
 #endif
-      return;
+      return NULL;
     }
       
     case ISD::SDIV:
@@ -902,7 +901,8 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
       DEBUG(std::cerr << "\n");
       Indent -= 2;
 #endif
-      return;
+
+      return NULL;
     }
 
     case ISD::TRUNCATE: {
@@ -927,7 +927,6 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
         AddToQueue(Tmp0, Node->getOperand(0));
         Tmp1 = SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0);
         Result = SDOperand(CurDAG->getTargetNode(Opc2, NVT, Tmp1), 0);
-        ReplaceUses(N, Result);
       
 #ifndef NDEBUG
         DEBUG(std::cerr << std::string(Indent-2, ' '));
@@ -936,14 +935,15 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
         DEBUG(std::cerr << "\n");
         Indent -= 2;
 #endif
-        return;
+        return Result.Val;
       }
 
       break;
     }
   }
 
-  SelectCode(Result, N);
+  SDNode *ResNode = SelectCode(Result, N);
+
 #ifndef NDEBUG
   DEBUG(std::cerr << std::string(Indent-2, ' '));
   DEBUG(std::cerr << "=> ");
@@ -951,6 +951,8 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
   DEBUG(std::cerr << "\n");
   Indent -= 2;
 #endif
+
+  return ResNode;
 }
 
 bool X86DAGToDAGISel::
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4b074700225..69b3dea0302 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2992,9 +2992,14 @@ SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
   }
   Constant *CS = ConstantStruct::get(CV);
   SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
-  SDOperand Mask 
-    = DAG.getNode(X86ISD::LOAD_PACK,
-                  VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+  std::vector<MVT::ValueType> Tys;
+  Tys.push_back(VT);
+  Tys.push_back(MVT::Other);
+  SmallVector<SDOperand, 3> Ops;
+  Ops.push_back(DAG.getEntryNode());
+  Ops.push_back(CPIdx);
+  Ops.push_back(DAG.getSrcValue(NULL));
+  SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
   return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
 }
 
@@ -3013,8 +3018,14 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
   }
   Constant *CS = ConstantStruct::get(CV);
   SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
-  SDOperand Mask  = DAG.getNode(X86ISD::LOAD_PACK,
-                          VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+  std::vector<MVT::ValueType> Tys;
+  Tys.push_back(VT);
+  Tys.push_back(MVT::Other);
+  SmallVector<SDOperand, 3> Ops;
+  Ops.push_back(DAG.getEntryNode());
+  Ops.push_back(CPIdx);
+  Ops.push_back(DAG.getSrcValue(NULL));
+  SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
   return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
 }
 
@@ -4121,10 +4132,15 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
                        Base->getOperand(2));
   else {
     // Just use movups, it's shorter.
+    std::vector<MVT::ValueType> Tys;
+    Tys.push_back(MVT::v4f32);
+    Tys.push_back(MVT::Other);
+    SmallVector<SDOperand, 3> Ops;
+    Ops.push_back(Base->getOperand(0));
+    Ops.push_back(Base->getOperand(1));
+    Ops.push_back(Base->getOperand(2));
     return DAG.getNode(ISD::BIT_CONVERT, VT,
-                       DAG.getNode(X86ISD::LOAD_UA, MVT::v4f32,
-                                   Base->getOperand(0), Base->getOperand(1),
-                                   Base->getOperand(2)));
+                       DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
   }
 }