diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86ScheduleZnver1.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 53 |
1 files changed, 16 insertions, 37 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index e9d265de3f8..4bd259775b8 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -188,9 +188,13 @@ def : WriteRes<WriteIMulH, [ZnALU1, ZnMultiplier]>{ } // Floating point operations -def : WriteRes<WriteFStore, [ZnAGU]>; -def : WriteRes<WriteFMove, [ZnFPU]>; -def : WriteRes<WriteFLoad, [ZnAGU]> { let Latency = 8; } +defm : X86WriteRes<WriteFLoad, [ZnAGU], 8, [1], 1>; +defm : X86WriteRes<WriteFMaskedLoad, [ZnAGU,ZnFPU01], 8, [1,1], 1>; +defm : X86WriteRes<WriteFMaskedLoadY, [ZnAGU,ZnFPU01], 8, [1,2], 2>; +defm : X86WriteRes<WriteFStore, [ZnAGU], 1, [1,1], 1>; +defm : X86WriteRes<WriteFMaskedStore, [ZnAGU,ZnFPU01], 4, [1,1], 1>; +defm : X86WriteRes<WriteFMaskedStoreY, [ZnAGU,ZnFPU01], 5, [1,2], 2>; +defm : X86WriteRes<WriteFMove, [ZnFPU], 1, [1], 1>; defm : ZnWriteResFpuPair<WriteFAdd, [ZnFPU0], 3>; defm : ZnWriteResFpuPair<WriteFAddX, [ZnFPU0], 3>; @@ -260,10 +264,14 @@ defm : ZnWriteResFpuPair<WriteFSqrt80, [ZnFPU3], 20, [20]>; def : WriteRes<WriteCvtF2FSt, [ZnFPU3, ZnAGU]>; // Vector integer operations which uses FPU units -def : WriteRes<WriteVecStore, [ZnAGU]>; -def : WriteRes<WriteVecMove, [ZnFPU]>; -def : WriteRes<WriteVecLoad, [ZnAGU]> { let Latency = 8; } -def : WriteRes<WriteEMMS, [ZnFPU]> { let Latency = 2; } +defm : X86WriteRes<WriteVecLoad, [ZnAGU], 8, [1], 1>; +defm : X86WriteRes<WriteVecMaskedLoad, [ZnAGU,ZnFPU01], 8, [1,2], 2>; +defm : X86WriteRes<WriteVecMaskedLoadY, [ZnAGU,ZnFPU01], 9, [1,3], 2>; +defm : X86WriteRes<WriteVecStore, [ZnAGU], 1, [1,1], 1>; +defm : X86WriteRes<WriteVecMaskedStore, [ZnAGU,ZnFPU01], 4, [1,1], 1>; +defm : X86WriteRes<WriteVecMaskedStoreY, [ZnAGU,ZnFPU01], 5, [1,2], 2>; +defm : X86WriteRes<WriteVecMove, [ZnFPU], 1, [1], 1>; +defm : X86WriteRes<WriteEMMS, [ZnFPU], 2, [1], 1>; defm : ZnWriteResFpuPair<WriteVecShift, [ZnFPU], 1>; defm : ZnWriteResFpuPair<WriteVecShiftX, [ZnFPU2], 1>; @@ -1030,11 +1038,8 @@ def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>; // MASKMOVDQU. def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>; -// VPMASKMOVQ. +// VPMASKMOVD. // ymm -def : InstRW<[ZnWriteFPU01Op2],(instregex "VPMASKMOVQrm")>; -def : InstRW<[ZnWriteFPU01Op2Y],(instregex "VPMASKMOVQYrm")>; - def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOVD(Y?)rm")>; // m, v,v. @@ -1168,32 +1173,6 @@ def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> { def : InstRW<[ZnWriteVINSERT128r], (instregex "VINSERTF128rr")>; def : InstRW<[ZnWriteVINSERT128Ld], (instregex "VINSERTF128rm")>; -// VMASKMOVP S/D. -// x,x,m. -def ZnWriteVMASKMOVPLd : SchedWriteRes<[ZnAGU, ZnFPU01]> { - let Latency = 8; -} -// y,y,m. -def ZnWriteVMASKMOVPLdY : SchedWriteRes<[ZnAGU, ZnFPU01]> { - let Latency = 8; - let NumMicroOps = 2; - let ResourceCycles = [1, 2]; -} -def ZnWriteVMASKMOVPm : SchedWriteRes<[ZnAGU, ZnFPU01]> { - let Latency = 4; -} -def : InstRW<[ZnWriteVMASKMOVPLd], (instregex "VMASKMOVP(S|D)rm")>; -def : InstRW<[ZnWriteVMASKMOVPLdY], (instregex "VMASKMOVP(S|D)Yrm")>; -def : InstRW<[ZnWriteVMASKMOVPm], (instregex "VMASKMOVP(S|D)mr")>; - -// m256,y,y. -def ZnWriteVMASKMOVPYmr : SchedWriteRes<[ZnAGU,ZnFPU01]> { - let Latency = 5; - let NumMicroOps = 2; - let ResourceCycles = [1, 2]; -} -def : InstRW<[ZnWriteVMASKMOVPYmr], (instregex "VMASKMOVP(S|D)Ymr")>; - // VGATHERDPS. // x. def : InstRW<[WriteMicrocoded], (instregex "VGATHERDPSrm")>; |
