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-rw-r--r--llvm/lib/Target/X86/X86ScheduleSLM.td113
1 files changed, 41 insertions, 72 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td
index 0292ce4af1f..8ba2cbcb984 100644
--- a/llvm/lib/Target/X86/X86ScheduleSLM.td
+++ b/llvm/lib/Target/X86/X86ScheduleSLM.td
@@ -56,15 +56,21 @@ def : ReadAdvance<ReadAfterLd, 3>;
// This multiclass defines the resource usage for variants with and without
// folded loads.
multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
- ProcResourceKind ExePort,
- int Lat> {
+ list<ProcResourceKind> ExePorts,
+ int Lat, list<int> Res = [1], int UOps = 1> {
// Register variant is using a single cycle on ExePort.
- def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
+ def : WriteRes<SchedRW, ExePorts> {
+ let Latency = Lat;
+ let ResourceCycles = Res;
+ let NumMicroOps = UOps;
+ }
// Memory variant also uses a cycle on MEC_RSV and adds 3 cycles to the
// latency.
- def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
- let Latency = !add(Lat, 3);
+ def : WriteRes<SchedRW.Folded, !listconcat([MEC_RSV], ExePorts)> {
+ let Latency = !add(Lat, 3);
+ let ResourceCycles = !listconcat([1], Res);
+ let NumMicroOps = UOps;
}
}
@@ -80,10 +86,10 @@ def : WriteRes<WriteZero, []>;
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
-defm : SMWriteResPair<WriteALU, IEC_RSV01, 1>;
-defm : SMWriteResPair<WriteIMul, IEC_RSV1, 3>;
-defm : SMWriteResPair<WriteShift, IEC_RSV0, 1>;
-defm : SMWriteResPair<WriteJump, IEC_RSV1, 1>;
+defm : SMWriteResPair<WriteALU, [IEC_RSV01], 1>;
+defm : SMWriteResPair<WriteIMul, [IEC_RSV1], 3>;
+defm : SMWriteResPair<WriteShift, [IEC_RSV0], 1>;
+defm : SMWriteResPair<WriteJump, [IEC_RSV1], 1>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
@@ -105,74 +111,37 @@ def : WriteRes<WriteFStore, [FPC_RSV01, MEC_RSV]>;
def : WriteRes<WriteFLoad, [MEC_RSV]> { let Latency = 3; }
def : WriteRes<WriteFMove, [FPC_RSV01]>;
-defm : SMWriteResPair<WriteFAdd, FPC_RSV1, 3>;
-defm : SMWriteResPair<WriteFRcp, FPC_RSV0, 5>;
-defm : SMWriteResPair<WriteFRsqrt, FPC_RSV0, 5>;
-defm : SMWriteResPair<WriteFSqrt, FPC_RSV0, 15>;
-defm : SMWriteResPair<WriteCvtF2I, FPC_RSV01, 4>;
-defm : SMWriteResPair<WriteCvtI2F, FPC_RSV01, 4>;
-defm : SMWriteResPair<WriteCvtF2F, FPC_RSV01, 4>;
-defm : SMWriteResPair<WriteFShuffle, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteFBlend, FPC_RSV0, 1>;
-
-// This is quite rough, latency depends on precision
-def : WriteRes<WriteFMul, [FPC_RSV0, SMFPMultiplier]> {
- let Latency = 5;
- let ResourceCycles = [1, 2];
-}
-def : WriteRes<WriteFMulLd, [MEC_RSV, FPC_RSV0, SMFPMultiplier]> {
- let Latency = 8;
- let ResourceCycles = [1, 1, 2];
-}
-
-def : WriteRes<WriteFDiv, [FPC_RSV0, SMFPDivider]> {
- let Latency = 34;
- let ResourceCycles = [1, 34];
-}
-def : WriteRes<WriteFDivLd, [MEC_RSV, FPC_RSV0, SMFPDivider]> {
- let Latency = 37;
- let ResourceCycles = [1, 1, 34];
-}
+defm : SMWriteResPair<WriteFAdd, [FPC_RSV1], 3>;
+defm : SMWriteResPair<WriteFMul, [FPC_RSV0, SMFPMultiplier], 5, [1,2]>;
+defm : SMWriteResPair<WriteFDiv, [FPC_RSV0, SMFPDivider], 34, [1,34]>;
+defm : SMWriteResPair<WriteFRcp, [FPC_RSV0], 5>;
+defm : SMWriteResPair<WriteFRsqrt, [FPC_RSV0], 5>;
+defm : SMWriteResPair<WriteFSqrt, [FPC_RSV0], 15>;
+defm : SMWriteResPair<WriteCvtF2I, [FPC_RSV01], 4>;
+defm : SMWriteResPair<WriteCvtI2F, [FPC_RSV01], 4>;
+defm : SMWriteResPair<WriteCvtF2F, [FPC_RSV01], 4>;
+defm : SMWriteResPair<WriteFShuffle, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteFBlend, [FPC_RSV0], 1>;
// Vector integer operations.
def : WriteRes<WriteVecStore, [FPC_RSV01, MEC_RSV]>;
def : WriteRes<WriteVecLoad, [MEC_RSV]> { let Latency = 3; }
def : WriteRes<WriteVecMove, [FPC_RSV01]>;
-defm : SMWriteResPair<WriteVecShift, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteVecLogic, FPC_RSV01, 1>;
-defm : SMWriteResPair<WriteVecALU, FPC_RSV01, 1>;
-defm : SMWriteResPair<WriteVecIMul, FPC_RSV0, 4>;
-defm : SMWriteResPair<WriteShuffle, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteBlend, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteMPSAD, FPC_RSV0, 7>;
+defm : SMWriteResPair<WriteVecShift, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteVecLogic, [FPC_RSV01], 1>;
+defm : SMWriteResPair<WriteVecALU, [FPC_RSV01], 1>;
+defm : SMWriteResPair<WriteVecIMul, [FPC_RSV0], 4>;
+defm : SMWriteResPair<WriteShuffle, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteBlend, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteMPSAD, [FPC_RSV0], 7>;
////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
-// HADD, HSUB PS/PD
-
-def : WriteRes<WriteFHAdd, [FPC_RSV01]> {
- let Latency = 3;
- let ResourceCycles = [2];
-}
-
-def : WriteRes<WriteFHAddLd, [FPC_RSV01, MEC_RSV]> {
- let Latency = 6;
- let ResourceCycles = [2, 1];
-}
-
-// PHADD|PHSUB (S) W/D.
-def : WriteRes<WritePHAdd, [FPC_RSV01]> {
- let Latency = 1;
- let ResourceCycles = [1];
-}
-
-def : WriteRes<WritePHAddLd, [FPC_RSV01, MEC_RSV]> {
- let Latency = 4;
- let ResourceCycles = [1, 1];
-}
+defm : SMWriteResPair<WriteFHAdd, [FPC_RSV01], 3, [2]>;
+defm : SMWriteResPair<WritePHAdd, [FPC_RSV01], 1>;
// String instructions.
// Packed Compare Implicit Length Strings, Return Mask
@@ -262,10 +231,10 @@ def : WriteRes<WriteNop, []>;
// AVX/FMA is not supported on that architecture, but we should define the basic
// scheduling resources anyway.
def : WriteRes<WriteIMulH, [FPC_RSV0]>;
-defm : SMWriteResPair<WriteVarBlend, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteFVarBlend, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteFShuffle256, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteShuffle256, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteVarVecShift, FPC_RSV0, 1>;
-defm : SMWriteResPair<WriteFMA, FPC_RSV0, 1>;
+defm : SMWriteResPair<WriteVarBlend, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteFVarBlend, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteFShuffle256, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteShuffle256, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteVarVecShift, [FPC_RSV0], 1>;
+defm : SMWriteResPair<WriteFMA, [FPC_RSV0], 1>;
} // SchedModel
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