diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86ScheduleBtVer2.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 36 |
1 files changed, 32 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 721088457a3..be77f885a28 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -555,7 +555,7 @@ def JWriteZeroLatency : SchedWriteRes<[]> { let Latency = 0; } -// Vector XOR instructions that use the same register for both source +// Certain vector instructions that use the same register for both source // operands do not have a real dependency on the previous contents of the // register, and thus, do not have to wait before completing. They can be // optimized out at register renaming stage. @@ -568,14 +568,42 @@ def JWriteFZeroIdiom : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, SchedVar<MCSchedPredicate<TruePred>, [WriteFLogic]> ]>; +def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr, + ANDNPSrr, VANDNPSrr, + ANDNPDrr, VANDNPDrr)>; -def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr)>; +def JWriteVZeroIdiomLogic : SchedWriteVariant<[ + SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, + SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]> +]>; +def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>; -def JWriteVZeroIdiom : SchedWriteVariant<[ +def JWriteVZeroIdiomLogicX : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogicX]> ]>; +def : InstRW<[JWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, + PANDNrr, VPANDNrr)>; -def : InstRW<[JWriteVZeroIdiom], (instrs PXORrr, VPXORrr)>; +def JWriteVZeroIdiomALU : SchedWriteVariant<[ + SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, + SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]> +]>; +def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr, + MMX_PSUBQirr, MMX_PSUBWirr, + MMX_PCMPGTBirr, MMX_PCMPGTDirr, + MMX_PCMPGTWirr)>; +def JWriteVZeroIdiomALUX : SchedWriteVariant<[ + SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, + SchedVar<MCSchedPredicate<TruePred>, [WriteVecALUX]> +]>; +def : InstRW<[JWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, + PSUBDrr, VPSUBDrr, + PSUBQrr, VPSUBQrr, + PSUBWrr, VPSUBWrr, + PCMPGTBrr, VPCMPGTBrr, + PCMPGTDrr, VPCMPGTDrr, + PCMPGTQrr, VPCMPGTQrr, + PCMPGTWrr, VPCMPGTWrr)>; } // SchedModel |
