1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index f92818e4f39..88a85609fbd 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -129,6 +129,29 @@ def  : WriteRes<WriteIMulH, [JALU1]> {
 // FIXME: SAGU 3-operand LEA
 def : WriteRes<WriteLEA, [JALU01]>;
 
+// FIXME: Why do bitcounts use WriteIMul?
+def JWriteLZCNT : SchedWriteRes<[JALU01]> {
+  let Latency = 1;
+}
+def JWriteLZCNTLd : SchedWriteRes<[JLAGU, JALU01]> {
+  let Latency = 4;
+}
+def : InstRW<[JWriteLZCNT], (instrs LZCNT16rr, LZCNT32rr, LZCNT64rr,
+                                    POPCNT16rr, POPCNT32rr, POPCNT64rr)>;
+def : InstRW<[JWriteLZCNTLd], (instrs LZCNT16rm, LZCNT32rm, LZCNT64rm,
+                                    POPCNT16rm, POPCNT32rm, POPCNT64rm)>;
+
+def JWriteTZCNT : SchedWriteRes<[JALU01]> {
+  let Latency = 2;
+  let ResourceCycles = [2];
+}
+def JWriteTZCNTLd : SchedWriteRes<[JLAGU, JALU01]> {
+  let Latency = 5;
+  let ResourceCycles = [1, 2];
+}
+def : InstRW<[JWriteTZCNT], (instrs TZCNT16rr, TZCNT32rr, TZCNT64rr)>;
+def : InstRW<[JWriteTZCNTLd], (instrs TZCNT16rm, TZCNT32rm, TZCNT64rm)>;
+
 def JWriteIDiv8 : SchedWriteRes<[JALU1, JDiv]> {
   let Latency = 12;
   let ResourceCycles = [1, 12];