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-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td138
1 files changed, 7 insertions, 131 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index df349202795..aa2a8b24870 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -160,6 +160,8 @@ defm : SKXWriteResPair<WriteFSqrt, [SKXPort0], 15>; // Floating point square ro
defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 5>; // Floating point reciprocal estimate.
defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 5>; // Floating point reciprocal square root estimate.
defm : SKXWriteResPair<WriteFMA, [SKXPort015], 4>; // Fused Multiply Add.
+defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
+defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1>; // Floating point vector shuffles.
defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1>; // Floating point vector variable shuffles.
defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1>; // Floating point vector blends.
@@ -174,6 +176,7 @@ def : WriteRes<WriteVecStore, [SKXPort237, SKXPort4]>;
def : WriteRes<WriteVecMove, [SKXPort015]>;
defm : SKXWriteResPair<WriteVecALU, [SKXPort15], 1>; // Vector integer ALU op, no logicals.
+defm : SKXWriteResPair<WriteVecLogic, [SKXPort015], 1, [1], 1, 6>; // Vector integer and/or/xor.
defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1>; // Vector integer shifts.
defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5>; // Vector integer multiply.
defm : SKXWriteResPair<WritePMULLD, [SKXPort015], 10, [2], 2, 6>; // Vector integer multiply.
@@ -184,10 +187,6 @@ defm : SKXWriteResPair<WriteVarBlend, [SKXPort5], 2, [2]>; // Vector variable b
defm : SKXWriteResPair<WriteMPSAD, [SKXPort0, SKXPort5], 6, [1, 2]>; // Vector MPSAD.
defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3>; // Vector PSADBW.
-// Vector bitwise operations.
-// These are often used on both floating point and integer vectors.
-defm : SKXWriteResPair<WriteVecLogic, [SKXPort015], 1>; // Vector and/or/xor.
-
// Conversion between integer and float.
defm : SKXWriteResPair<WriteCvtF2I, [SKXPort1], 3>; // Float -> Integer.
defm : SKXWriteResPair<WriteCvtI2F, [SKXPort1], 4>; // Integer -> Float.
@@ -1026,11 +1025,7 @@ def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
- "ANDNPSrr",
- "ANDPDrr",
- "ANDPSrr",
- "BLENDPDrri",
+def: InstRW<[SKXWriteResGroup9], (instregex "BLENDPDrri",
"BLENDPSrri",
"MOVAPDrr",
"MOVAPSrr",
@@ -1039,40 +1034,14 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"MOVPQI2QIrr",
"MOVUPDrr",
"MOVUPSrr",
- "ORPDrr",
- "ORPSrr",
"PADDBrr",
"PADDDrr",
"PADDQrr",
"PADDWrr",
- "PANDNrr",
- "PANDrr",
- "PORrr",
"PSUBBrr",
"PSUBDrr",
"PSUBQrr",
"PSUBWrr",
- "PXORrr",
- "VANDNPDYrr",
- "VANDNPDZ128rr",
- "VANDNPDZ256rr",
- "VANDNPDZrr",
- "VANDNPDrr",
- "VANDNPSYrr",
- "VANDNPSZ128rr",
- "VANDNPSZ256rr",
- "VANDNPSZrr",
- "VANDNPSrr",
- "VANDPDYrr",
- "VANDPDZ128rr",
- "VANDPDZ256rr",
- "VANDPDZrr",
- "VANDPDrr",
- "VANDPSYrr",
- "VANDPSZ128rr",
- "VANDPSZ256rr",
- "VANDPSZrr",
- "VANDPSrr",
"VBLENDMPDZ128rr",
"VBLENDMPDZ256rr",
"VBLENDMPDZrr",
@@ -1128,16 +1097,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VMOVUPSYrr",
"VMOVUPSrr",
"VMOVZPQILo2PQIrr",
- "VORPDYrr",
- "VORPDZ128rr",
- "VORPDZ256rr",
- "VORPDZrr",
- "VORPDrr",
- "VORPSYrr",
- "VORPSZ128rr",
- "VORPSZ256rr",
- "VORPSZrr",
- "VORPSrr",
"VPADDBYrr",
"VPADDBZ128rr",
"VPADDBZ256rr",
@@ -1158,22 +1117,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VPADDWZ256rr",
"VPADDWZrr",
"VPADDWrr",
- "VPANDDZ128rr",
- "VPANDDZ256rr",
- "VPANDDZrr",
- "VPANDNDZ128rr",
- "VPANDNDZ256rr",
- "VPANDNDZrr",
- "VPANDNQZ128rr",
- "VPANDNQZ256rr",
- "VPANDNQZrr",
- "VPANDNYrr",
- "VPANDNrr",
- "VPANDQZ128rr",
- "VPANDQZ256rr",
- "VPANDQZrr",
- "VPANDYrr",
- "VPANDrr",
"VPBLENDDYrri",
"VPBLENDDrri",
"VPBLENDMBZ128rr",
@@ -1188,14 +1131,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VPBLENDMWZ128rr",
"VPBLENDMWZ256rr",
"VPBLENDMWZrr",
- "VPORDZ128rr",
- "VPORDZ256rr",
- "VPORDZrr",
- "VPORQZ128rr",
- "VPORQZ256rr",
- "VPORQZrr",
- "VPORYrr",
- "VPORrr",
"VPSUBBYrr",
"VPSUBBZ128rr",
"VPSUBBZ256rr",
@@ -1220,27 +1155,7 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VPTERNLOGDZrri",
"VPTERNLOGQZ128rri",
"VPTERNLOGQZ256rri",
- "VPTERNLOGQZrri",
- "VPXORDZ128rr",
- "VPXORDZ256rr",
- "VPXORDZrr",
- "VPXORQZ128rr",
- "VPXORQZ256rr",
- "VPXORQZrr",
- "VPXORYrr",
- "VPXORrr",
- "VXORPDYrr",
- "VXORPDZ128rr",
- "VXORPDZ256rr",
- "VXORPDZrr",
- "VXORPDrr",
- "VXORPSYrr",
- "VXORPSZ128rr",
- "VXORPSZ256rr",
- "VXORPSZrr",
- "VXORPSrr",
- "XORPDrr",
- "XORPSrr")>;
+ "VPTERNLOGQZrri")>;
def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let Latency = 1;
@@ -3346,34 +3261,16 @@ def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
- "ANDNPSrm",
- "ANDPDrm",
- "ANDPSrm",
- "BLENDPDrmi",
+def: InstRW<[SKXWriteResGroup95], (instregex "BLENDPDrmi",
"BLENDPSrmi",
- "ORPDrm",
- "ORPSrm",
"PADDBrm",
"PADDDrm",
"PADDQrm",
"PADDWrm",
- "PANDNrm",
- "PANDrm",
- "PORrm",
"PSUBBrm",
"PSUBDrm",
"PSUBQrm",
"PSUBWrm",
- "PXORrm",
- "VANDNPDZ128rm(b?)",
- "VANDNPDrm",
- "VANDNPSZ128rm(b?)",
- "VANDNPSrm",
- "VANDPDZ128rm(b?)",
- "VANDPDrm",
- "VANDPSZ128rm(b?)",
- "VANDPSrm",
"VBLENDMPDZ128rm(b?)",
"VBLENDMPSZ128rm(b?)",
"VBLENDPDrmi",
@@ -3398,10 +3295,6 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VMOVSLDUPZ128rm(b?)",
"VMOVUPDZ128rm(b?)",
"VMOVUPSZ128rm(b?)",
- "VORPDZ128rm(b?)",
- "VORPDrm",
- "VORPSZ128rm(b?)",
- "VORPSrm",
"VPADDBZ128rm(b?)",
"VPADDBrm",
"VPADDDZ128rm(b?)",
@@ -3410,12 +3303,6 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VPADDQrm",
"VPADDWZ128rm(b?)",
"VPADDWrm",
- "VPANDDZ128rm(b?)",
- "VPANDNDZ128rm(b?)",
- "VPANDNQZ128rm(b?)",
- "VPANDNrm",
- "VPANDQZ128rm(b?)",
- "VPANDrm",
"VPBLENDDrmi",
"VPBLENDMBZ128rm(b?)",
"VPBLENDMDZ128rm(b?)",
@@ -3425,8 +3312,6 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VPBROADCASTQZ128m(b?)",
"VPMASKMOVDrm",
"VPMASKMOVQrm",
- "VPORDZ128rm(b?)",
- "VPORQZ128rm(b?)",
"VPORrm",
"VPSUBBZ128rm(b?)",
"VPSUBBrm",
@@ -3437,16 +3322,7 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VPSUBWZ128rm(b?)",
"VPSUBWrm",
"VPTERNLOGDZ128rm(b?)i",
- "VPTERNLOGQZ128rm(b?)i",
- "VPXORDZ128rm(b?)",
- "VPXORQZ128rm(b?)",
- "VPXORrm",
- "VXORPDZ128rm(b?)",
- "VXORPDrm",
- "VXORPSZ128rm(b?)",
- "VXORPSrm",
- "XORPDrm",
- "XORPSrm")>;
+ "VPTERNLOGQZ128rm(b?)i")>;
def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 7;
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