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-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td8
1 files changed, 1 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 8dc684f5591..3066dbb22c3 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -754,13 +754,7 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",
"BTR(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
- "BTS(16|32|64)rr",
- "SAR(8|16|32|64)r1",
- "SAR(8|16|32|64)ri",
- "SHL(8|16|32|64)r1",
- "SHL(8|16|32|64)ri",
- "SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri")>;
+ "BTS(16|32|64)rr")>;
def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
let Latency = 1;
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