diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedBroadwell.td')
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 47 |
1 files changed, 18 insertions, 29 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 0efdd971690..a1624b0c968 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -123,14 +123,24 @@ defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>; defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>; def : WriteRes<WriteIMulH, []> { let Latency = 3; } -defm : BWWriteResPair<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10]>; -defm : BWWriteResPair<WriteDiv16, [BWPort0, BWDivider], 25, [1, 10]>; -defm : BWWriteResPair<WriteDiv32, [BWPort0, BWDivider], 25, [1, 10]>; -defm : BWWriteResPair<WriteDiv64, [BWPort0, BWDivider], 25, [1, 10]>; -defm : BWWriteResPair<WriteIDiv8, [BWPort0, BWDivider], 25, [1, 10]>; -defm : BWWriteResPair<WriteIDiv16, [BWPort0, BWDivider], 25, [1, 10]>; -defm : BWWriteResPair<WriteIDiv32, [BWPort0, BWDivider], 25, [1, 10]>; -defm : BWWriteResPair<WriteIDiv64, [BWPort0, BWDivider], 25, [1, 10]>; +// TODO: Why isn't the BWDivider used consistently? +defm : X86WriteRes<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10], 1>; +defm : X86WriteRes<WriteDiv16, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; +defm : X86WriteRes<WriteDiv32, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; +defm : X86WriteRes<WriteDiv64, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; +defm : X86WriteRes<WriteDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; +defm : X86WriteRes<WriteDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; +defm : X86WriteRes<WriteDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; +defm : X86WriteRes<WriteDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; + +defm : X86WriteRes<WriteIDiv8, [BWPort0, BWDivider], 25, [1,10], 1>; +defm : X86WriteRes<WriteIDiv16, [BWPort0, BWDivider], 25, [1,10], 1>; +defm : X86WriteRes<WriteIDiv32, [BWPort0, BWDivider], 25, [1,10], 1>; +defm : X86WriteRes<WriteIDiv64, [BWPort0, BWDivider], 25, [1,10], 1>; +defm : X86WriteRes<WriteIDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; +defm : X86WriteRes<WriteIDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; +defm : X86WriteRes<WriteIDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; +defm : X86WriteRes<WriteIDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>; defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>; @@ -1520,13 +1530,6 @@ def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPor def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; -def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> { - let Latency = 34; - let NumMicroOps = 8; - let ResourceCycles = [2,2,2,1,1]; -} -def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>; - def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { let Latency = 34; let NumMicroOps = 23; @@ -1535,13 +1538,6 @@ def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", "IN(8|16|32)rr")>; -def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> { - let Latency = 35; - let NumMicroOps = 8; - let ResourceCycles = [2,2,2,1,1]; -} -def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>; - def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { let Latency = 35; let NumMicroOps = 23; @@ -1585,13 +1581,6 @@ def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { } def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; -def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> { - let Latency = 80; - let NumMicroOps = 32; - let ResourceCycles = [7,7,3,3,1,11]; -} -def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>; - def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { let Latency = 115; let NumMicroOps = 100; |
