diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrFragmentsSIMD.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 53 |
1 files changed, 23 insertions, 30 deletions
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index 3aa825ee84e..f750fe3ee0c 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -647,28 +647,22 @@ def sdmem : Operand<v2f64> { // SSE pattern fragments //===----------------------------------------------------------------------===// -// Vector load wrappers to prevent folding of non-temporal aligned loads on -// supporting targets. -def vecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return !useNonTemporalLoad(cast<LoadSDNode>(N)); -}]>; - // 128-bit load pattern fragments // NOTE: all 128-bit integer vector loads are promoted to v2i64 -def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (vecload node:$ptr))>; -def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (vecload node:$ptr))>; -def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (vecload node:$ptr))>; +def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; +def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; +def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; // 256-bit load pattern fragments // NOTE: all 256-bit integer vector loads are promoted to v4i64 -def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (vecload node:$ptr))>; -def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (vecload node:$ptr))>; -def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (vecload node:$ptr))>; +def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; +def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; +def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; // 512-bit load pattern fragments -def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (vecload node:$ptr))>; -def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (vecload node:$ptr))>; -def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (vecload node:$ptr))>; +def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>; +def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>; +def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>; // 128-/256-/512-bit extload pattern fragments def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>; @@ -682,46 +676,45 @@ def alignedstore : PatFrag<(ops node:$val, node:$ptr), return St->getAlignment() >= St->getMemoryVT().getStoreSize(); }]>; -// Like 'load', but always requires 128-bit vector alignment. -def alignedvecload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ +// Like 'load', but always requires vector size alignment. +def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ auto *Ld = cast<LoadSDNode>(N); - return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize() && - !useNonTemporalLoad(cast<LoadSDNode>(N)); + return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); }]>; // 128-bit aligned load pattern fragments // NOTE: all 128-bit integer vector loads are promoted to v2i64 def alignedloadv4f32 : PatFrag<(ops node:$ptr), - (v4f32 (alignedvecload node:$ptr))>; + (v4f32 (alignedload node:$ptr))>; def alignedloadv2f64 : PatFrag<(ops node:$ptr), - (v2f64 (alignedvecload node:$ptr))>; + (v2f64 (alignedload node:$ptr))>; def alignedloadv2i64 : PatFrag<(ops node:$ptr), - (v2i64 (alignedvecload node:$ptr))>; + (v2i64 (alignedload node:$ptr))>; // 256-bit aligned load pattern fragments // NOTE: all 256-bit integer vector loads are promoted to v4i64 def alignedloadv8f32 : PatFrag<(ops node:$ptr), - (v8f32 (alignedvecload node:$ptr))>; + (v8f32 (alignedload node:$ptr))>; def alignedloadv4f64 : PatFrag<(ops node:$ptr), - (v4f64 (alignedvecload node:$ptr))>; + (v4f64 (alignedload node:$ptr))>; def alignedloadv4i64 : PatFrag<(ops node:$ptr), - (v4i64 (alignedvecload node:$ptr))>; + (v4i64 (alignedload node:$ptr))>; // 512-bit aligned load pattern fragments def alignedloadv16f32 : PatFrag<(ops node:$ptr), - (v16f32 (alignedvecload node:$ptr))>; + (v16f32 (alignedload node:$ptr))>; def alignedloadv8f64 : PatFrag<(ops node:$ptr), - (v8f64 (alignedvecload node:$ptr))>; + (v8f64 (alignedload node:$ptr))>; def alignedloadv8i64 : PatFrag<(ops node:$ptr), - (v8i64 (alignedvecload node:$ptr))>; + (v8i64 (alignedload node:$ptr))>; -// Like 'vecload', but uses special alignment checks suitable for use in +// Like 'load', but uses special alignment checks suitable for use in // memory operands in most SSE instructions, which are required to // be naturally aligned on some targets but not on others. If the subtarget // allows unaligned accesses, match any load, though this may require // setting a feature bit in the processor (on startup, for example). // Opteron 10h and later implement such a feature. -def memop : PatFrag<(ops node:$ptr), (vecload node:$ptr), [{ +def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ auto *Ld = cast<LoadSDNode>(N); return Subtarget->hasSSEUnalignedMem() || Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); |
