diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrAVX512.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index bb189698e80..8cb1cb8a416 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6530,16 +6530,16 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT, X86VectorVTInfo DstVT, SDNode OpNode, OpndItins itins, string asm> { let Predicates = [HasAVX512] in { - def rr : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src), + def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src), !strconcat(asm,"\t{$src, $dst|$dst, $src}"), [(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 FROUND_CURRENT)))], itins.rr>, EVEX, VEX_LIG, Sched<[itins.Sched]>; - def rrb : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc), + def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc), !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), [(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))], itins.rr>, EVEX, VEX_LIG, EVEX_B, EVEX_RC, Sched<[itins.Sched]>; - def rm : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.IntScalarMemOp:$src), + def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.IntScalarMemOp:$src), !strconcat(asm,"\t{$src, $dst|$dst, $src}"), [(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.ScalarIntMemCPat:$src), @@ -6578,21 +6578,21 @@ defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info, // Therefore, the SSE intrinsics are mapped to the AVX512 instructions. let Predicates = [HasAVX512] in { def : Pat<(i32 (int_x86_sse_cvtss2si (v4f32 VR128X:$src))), - (VCVTSS2SIZrr VR128X:$src)>; + (VCVTSS2SIZrr_Int VR128X:$src)>; def : Pat<(i32 (int_x86_sse_cvtss2si sse_load_f32:$src)), - (VCVTSS2SIZrm sse_load_f32:$src)>; + (VCVTSS2SIZrm_Int sse_load_f32:$src)>; def : Pat<(i64 (int_x86_sse_cvtss2si64 (v4f32 VR128X:$src))), - (VCVTSS2SI64Zrr VR128X:$src)>; + (VCVTSS2SI64Zrr_Int VR128X:$src)>; def : Pat<(i64 (int_x86_sse_cvtss2si64 sse_load_f32:$src)), - (VCVTSS2SI64Zrm sse_load_f32:$src)>; + (VCVTSS2SI64Zrm_Int sse_load_f32:$src)>; def : Pat<(i32 (int_x86_sse2_cvtsd2si (v2f64 VR128X:$src))), - (VCVTSD2SIZrr VR128X:$src)>; + (VCVTSD2SIZrr_Int VR128X:$src)>; def : Pat<(i32 (int_x86_sse2_cvtsd2si sse_load_f64:$src)), - (VCVTSD2SIZrm sse_load_f64:$src)>; + (VCVTSD2SIZrm_Int sse_load_f64:$src)>; def : Pat<(i64 (int_x86_sse2_cvtsd2si64 (v2f64 VR128X:$src))), - (VCVTSD2SI64Zrr VR128X:$src)>; + (VCVTSD2SI64Zrr_Int VR128X:$src)>; def : Pat<(i64 (int_x86_sse2_cvtsd2si64 sse_load_f64:$src)), - (VCVTSD2SI64Zrm sse_load_f64:$src)>; + (VCVTSD2SI64Zrm_Int sse_load_f64:$src)>; } // HasAVX512 let Predicates = [HasAVX512] in { |
