diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 152 |
1 files changed, 76 insertions, 76 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1ba801edf79..91ef663844c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -4457,7 +4457,7 @@ bool X86::isCalleePop(CallingConv::ID CallingConv, } } -/// \brief Return true if the condition is an unsigned comparison operation. +/// Return true if the condition is an unsigned comparison operation. static bool isX86CCUnsigned(unsigned X86CC) { switch (X86CC) { default: @@ -4666,7 +4666,7 @@ bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load, return true; } -/// \brief Returns true if it is beneficial to convert a load of a constant +/// Returns true if it is beneficial to convert a load of a constant /// to just the constant itself. bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const { @@ -4856,7 +4856,7 @@ static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos, return true; } -/// \brief Helper function to test whether a shuffle mask could be +/// Helper function to test whether a shuffle mask could be /// simplified by widening the elements being shuffled. /// /// Appends the mask for wider elements in WidenedMask if valid. Otherwise @@ -7151,7 +7151,7 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp, return SDValue(); } -/// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real +/// For an EXTRACT_VECTOR_ELT with a constant index return the real /// underlying vector and index. /// /// Modifies \p ExtractedFromVec to the real vector and returns the real @@ -7364,7 +7364,7 @@ static SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG, return DstVec; } -/// \brief Return true if \p N implements a horizontal binop and return the +/// Return true if \p N implements a horizontal binop and return the /// operands for the horizontal binop into V0 and V1. /// /// This is a helper function of LowerToHorizontalOp(). @@ -7461,7 +7461,7 @@ static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode, return CanFold; } -/// \brief Emit a sequence of two 128-bit horizontal add/sub followed by +/// Emit a sequence of two 128-bit horizontal add/sub followed by /// a concat_vector. /// /// This is a helper function of LowerToHorizontalOp(). @@ -8822,7 +8822,7 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op, // patterns. //===----------------------------------------------------------------------===// -/// \brief Tiny helper function to identify a no-op mask. +/// Tiny helper function to identify a no-op mask. /// /// This is a somewhat boring predicate function. It checks whether the mask /// array input, which is assumed to be a single-input shuffle mask of the kind @@ -8838,7 +8838,7 @@ static bool isNoopShuffleMask(ArrayRef<int> Mask) { return true; } -/// \brief Test whether there are elements crossing 128-bit lanes in this +/// Test whether there are elements crossing 128-bit lanes in this /// shuffle mask. /// /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations @@ -8852,7 +8852,7 @@ static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) { return false; } -/// \brief Test whether a shuffle mask is equivalent within each sub-lane. +/// Test whether a shuffle mask is equivalent within each sub-lane. /// /// This checks a shuffle mask to see if it is performing the same /// lane-relative shuffle in each sub-lane. This trivially implies @@ -8941,7 +8941,7 @@ static bool isRepeatedTargetShuffleMask(unsigned LaneSizeInBits, MVT VT, return true; } -/// \brief Checks whether a shuffle mask is equivalent to an explicit list of +/// Checks whether a shuffle mask is equivalent to an explicit list of /// arguments. /// /// This is a fast way to test a shuffle mask against a fixed pattern: @@ -9038,7 +9038,7 @@ static bool isUnpackWdShuffleMask(ArrayRef<int> Mask, MVT VT) { return IsUnpackwdMask; } -/// \brief Get a 4-lane 8-bit shuffle immediate for a mask. +/// Get a 4-lane 8-bit shuffle immediate for a mask. /// /// This helper function produces an 8-bit shuffle immediate corresponding to /// the ubiquitous shuffle encoding scheme used in x86 instructions for @@ -9066,7 +9066,7 @@ static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, const SDLoc &DL, return DAG.getConstant(getV4X86ShuffleImm(Mask), DL, MVT::i8); } -/// \brief Compute whether each element of a shuffle is zeroable. +/// Compute whether each element of a shuffle is zeroable. /// /// A "zeroable" vector shuffle element is one which can be lowered to zero. /// Either it is an undef element in the shuffle mask, the element of the input @@ -9443,7 +9443,7 @@ static SDValue lowerVectorShuffleWithPACK(const SDLoc &DL, MVT VT, return SDValue(); } -/// \brief Try to emit a bitmask instruction for a shuffle. +/// Try to emit a bitmask instruction for a shuffle. /// /// This handles cases where we can model a blend exactly as a bitmask due to /// one of the inputs being zeroable. @@ -9476,7 +9476,7 @@ static SDValue lowerVectorShuffleAsBitMask(const SDLoc &DL, MVT VT, SDValue V1, return DAG.getNode(ISD::AND, DL, VT, V, VMask); } -/// \brief Try to emit a blend instruction for a shuffle using bit math. +/// Try to emit a blend instruction for a shuffle using bit math. /// /// This is used as a fallback approach when first class blend instructions are /// unavailable. Currently it is only suitable for integer vectors, but could @@ -9563,7 +9563,7 @@ static uint64_t scaleVectorShuffleBlendMask(uint64_t BlendMask, int Size, return ScaledMask; } -/// \brief Try to emit a blend instruction for a shuffle. +/// Try to emit a blend instruction for a shuffle. /// /// This doesn't do any checks for the availability of instructions for blending /// these values. It relies on the availability of the X86ISD::BLENDI pattern to @@ -9709,7 +9709,7 @@ static SDValue lowerVectorShuffleAsBlend(const SDLoc &DL, MVT VT, SDValue V1, } } -/// \brief Try to lower as a blend of elements from two inputs followed by +/// Try to lower as a blend of elements from two inputs followed by /// a single-input permutation. /// /// This matches the pattern where we can blend elements from two inputs and @@ -9741,7 +9741,7 @@ static SDValue lowerVectorShuffleAsBlendAndPermute(const SDLoc &DL, MVT VT, return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask); } -/// \brief Generic routine to decompose a shuffle and blend into independent +/// Generic routine to decompose a shuffle and blend into independent /// blends and permutes. /// /// This matches the extremely common pattern for handling combined @@ -9782,7 +9782,7 @@ static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(const SDLoc &DL, return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask); } -/// \brief Try to lower a vector shuffle as a rotation. +/// Try to lower a vector shuffle as a rotation. /// /// This is used for support PALIGNR for SSSE3 or VALIGND/Q for AVX512. static int matchVectorShuffleAsRotate(SDValue &V1, SDValue &V2, @@ -9854,7 +9854,7 @@ static int matchVectorShuffleAsRotate(SDValue &V1, SDValue &V2, return Rotation; } -/// \brief Try to lower a vector shuffle as a byte rotation. +/// Try to lower a vector shuffle as a byte rotation. /// /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use @@ -9938,7 +9938,7 @@ static SDValue lowerVectorShuffleAsByteRotate(const SDLoc &DL, MVT VT, DAG.getNode(ISD::OR, DL, MVT::v16i8, LoShift, HiShift)); } -/// \brief Try to lower a vector shuffle as a dword/qword rotation. +/// Try to lower a vector shuffle as a dword/qword rotation. /// /// AVX512 has a VALIGND/VALIGNQ instructions that will do an arbitrary /// rotation of the concatenation of two vectors; This routine will @@ -9969,7 +9969,7 @@ static SDValue lowerVectorShuffleAsRotate(const SDLoc &DL, MVT VT, DAG.getConstant(Rotation, DL, MVT::i8)); } -/// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros). +/// Try to lower a vector shuffle as a bit shift (shifts in zeros). /// /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function @@ -10213,7 +10213,7 @@ static bool matchVectorShuffleAsINSERTQ(MVT VT, SDValue &V1, SDValue &V2, return false; } -/// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ. +/// Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ. static SDValue lowerVectorShuffleWithSSE4A(const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask, const APInt &Zeroable, @@ -10233,7 +10233,7 @@ static SDValue lowerVectorShuffleWithSSE4A(const SDLoc &DL, MVT VT, SDValue V1, return SDValue(); } -/// \brief Lower a vector shuffle as a zero or any extension. +/// Lower a vector shuffle as a zero or any extension. /// /// Given a specific number of elements, element bit width, and extension /// stride, produce either a zero or any extension based on the available @@ -10388,7 +10388,7 @@ static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend( return DAG.getBitcast(VT, InputV); } -/// \brief Try to lower a vector shuffle as a zero extension on any microarch. +/// Try to lower a vector shuffle as a zero extension on any microarch. /// /// This routine will try to do everything in its power to cleverly lower /// a shuffle which happens to match the pattern of a zero extend. It doesn't @@ -10516,7 +10516,7 @@ static SDValue lowerVectorShuffleAsZeroOrAnyExtend( return SDValue(); } -/// \brief Try to get a scalar value for a specific element of a vector. +/// Try to get a scalar value for a specific element of a vector. /// /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar. static SDValue getScalarValueForVectorElement(SDValue V, int Idx, @@ -10543,7 +10543,7 @@ static SDValue getScalarValueForVectorElement(SDValue V, int Idx, return SDValue(); } -/// \brief Helper to test for a load that can be folded with x86 shuffles. +/// Helper to test for a load that can be folded with x86 shuffles. /// /// This is particularly important because the set of instructions varies /// significantly based on whether the operand is a load or not. @@ -10552,7 +10552,7 @@ static bool isShuffleFoldableLoad(SDValue V) { return ISD::isNON_EXTLoad(V.getNode()); } -/// \brief Try to lower insertion of a single element into a zero vector. +/// Try to lower insertion of a single element into a zero vector. /// /// This is a common pattern that we have especially efficient patterns to lower /// across all subtarget feature sets. @@ -10705,7 +10705,7 @@ static SDValue lowerVectorShuffleAsTruncBroadcast(const SDLoc &DL, MVT VT, DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar)); } -/// \brief Try to lower broadcast of a single element. +/// Try to lower broadcast of a single element. /// /// For convenience, this code also bundles all of the subtarget feature set /// filtering. While a little annoying to re-dispatch on type here, there isn't @@ -11030,7 +11030,7 @@ static SDValue lowerVectorShuffleAsInsertPS(const SDLoc &DL, SDValue V1, DAG.getConstant(InsertPSMask, DL, MVT::i8)); } -/// \brief Try to lower a shuffle as a permute of the inputs followed by an +/// Try to lower a shuffle as a permute of the inputs followed by an /// UNPCK instruction. /// /// This specifically targets cases where we end up with alternating between @@ -11142,7 +11142,7 @@ static SDValue lowerVectorShuffleAsPermuteAndUnpack(const SDLoc &DL, MVT VT, return SDValue(); } -/// \brief Handle lowering of 2-lane 64-bit floating point shuffles. +/// Handle lowering of 2-lane 64-bit floating point shuffles. /// /// This is the basis function for the 2-lane 64-bit shuffles as we have full /// support for floating point shuffles but not integer shuffles. These @@ -11225,7 +11225,7 @@ static SDValue lowerV2F64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, DAG.getConstant(SHUFPDMask, DL, MVT::i8)); } -/// \brief Handle lowering of 2-lane 64-bit integer shuffles. +/// Handle lowering of 2-lane 64-bit integer shuffles. /// /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by /// the integer unit to minimize domain crossing penalties. However, for blends @@ -11322,7 +11322,7 @@ static SDValue lowerV2I64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask)); } -/// \brief Test whether this can be lowered with a single SHUFPS instruction. +/// Test whether this can be lowered with a single SHUFPS instruction. /// /// This is used to disable more specialized lowerings when the shufps lowering /// will happen to be efficient. @@ -11344,7 +11344,7 @@ static bool isSingleSHUFPSMask(ArrayRef<int> Mask) { return true; } -/// \brief Lower a vector shuffle using the SHUFPS instruction. +/// Lower a vector shuffle using the SHUFPS instruction. /// /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS. /// It makes no assumptions about whether this is the *best* lowering, it simply @@ -11431,7 +11431,7 @@ static SDValue lowerVectorShuffleWithSHUFPS(const SDLoc &DL, MVT VT, getV4X86ShuffleImm8ForMask(NewMask, DL, DAG)); } -/// \brief Lower 4-lane 32-bit floating point shuffles. +/// Lower 4-lane 32-bit floating point shuffles. /// /// Uses instructions exclusively from the floating point unit to minimize /// domain crossing penalties, as these are sufficient to implement all v4f32 @@ -11527,7 +11527,7 @@ static SDValue lowerV4F32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG); } -/// \brief Lower 4-lane i32 vector shuffles. +/// Lower 4-lane i32 vector shuffles. /// /// We try to handle these with integer-domain shuffles where we can, but for /// blends we use the floating point domain blend instructions. @@ -11639,7 +11639,7 @@ static SDValue lowerV4I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return DAG.getBitcast(MVT::v4i32, ShufPS); } -/// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2 +/// Lowering of single-input v8i16 shuffles is the cornerstone of SSE2 /// shuffle lowering, and the most complex part. /// /// The lowering strategy is to try to form pairs of input lanes which are @@ -12204,7 +12204,7 @@ static SDValue lowerVectorShuffleAsBlendOfPSHUFBs( return DAG.getBitcast(VT, V); } -/// \brief Generic lowering of 8-lane i16 shuffles. +/// Generic lowering of 8-lane i16 shuffles. /// /// This handles both single-input shuffles and combined shuffle/blends with /// two inputs. The single input shuffles are immediately delegated to @@ -12337,7 +12337,7 @@ static SDValue lowerV8I16VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, Mask, DAG); } -/// \brief Check whether a compaction lowering can be done by dropping even +/// Check whether a compaction lowering can be done by dropping even /// elements and compute how many times even elements must be dropped. /// /// This handles shuffles which take every Nth element where N is a power of @@ -12416,7 +12416,7 @@ static SDValue lowerVectorShuffleWithPERMV(const SDLoc &DL, MVT VT, return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2); } -/// \brief Generic lowering of v16i8 shuffles. +/// Generic lowering of v16i8 shuffles. /// /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to /// detect any complexity reducing interleaving. If that doesn't help, it uses @@ -12716,7 +12716,7 @@ static SDValue lowerV16I8VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV); } -/// \brief Dispatching routine to lower various 128-bit x86 vector shuffles. +/// Dispatching routine to lower various 128-bit x86 vector shuffles. /// /// This routine breaks down the specific type of 128-bit shuffle and /// dispatches to the lowering routines accordingly. @@ -12744,7 +12744,7 @@ static SDValue lower128BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, } } -/// \brief Generic routine to split vector shuffle into half-sized shuffles. +/// Generic routine to split vector shuffle into half-sized shuffles. /// /// This routine just extracts two subvectors, shuffles them independently, and /// then concatenates them back together. This should work effectively with all @@ -12867,7 +12867,7 @@ static SDValue splitAndLowerVectorShuffle(const SDLoc &DL, MVT VT, SDValue V1, return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); } -/// \brief Either split a vector in halves or decompose the shuffles and the +/// Either split a vector in halves or decompose the shuffles and the /// blend. /// /// This is provided as a good fallback for many lowerings of non-single-input @@ -12925,7 +12925,7 @@ static SDValue lowerVectorShuffleAsSplitOrBlend(const SDLoc &DL, MVT VT, return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG); } -/// \brief Lower a vector shuffle crossing multiple 128-bit lanes as +/// Lower a vector shuffle crossing multiple 128-bit lanes as /// a permutation and blend of those lanes. /// /// This essentially blends the out-of-lane inputs to each lane into the lane @@ -12983,7 +12983,7 @@ static SDValue lowerVectorShuffleAsLanePermuteAndBlend(const SDLoc &DL, MVT VT, return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask); } -/// \brief Handle lowering 2-lane 128-bit shuffles. +/// Handle lowering 2-lane 128-bit shuffles. static SDValue lowerV2X128VectorShuffle(const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask, const APInt &Zeroable, @@ -13079,7 +13079,7 @@ static SDValue lowerV2X128VectorShuffle(const SDLoc &DL, MVT VT, SDValue V1, DAG.getConstant(PermMask, DL, MVT::i8)); } -/// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then +/// Lower a vector shuffle by first fixing the 128-bit lanes and then /// shuffling each lane. /// /// This will only succeed when the result of fixing the 128-bit lanes results @@ -13282,7 +13282,7 @@ static SDValue lowerVectorShuffleWithUndefHalf(const SDLoc &DL, MVT VT, DAG.getIntPtrConstant(Offset, DL)); } -/// \brief Test whether the specified input (0 or 1) is in-place blended by the +/// Test whether the specified input (0 or 1) is in-place blended by the /// given mask. /// /// This returns true if the elements from a particular input are already in the @@ -13518,7 +13518,7 @@ static SDValue lowerVectorShuffleWithSHUFPD(const SDLoc &DL, MVT VT, DAG.getConstant(Immediate, DL, MVT::i8)); } -/// \brief Handle lowering of 4-lane 64-bit floating point shuffles. +/// Handle lowering of 4-lane 64-bit floating point shuffles. /// /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2 /// isn't available. @@ -13615,7 +13615,7 @@ static SDValue lowerV4F64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG); } -/// \brief Handle lowering of 4-lane 64-bit integer shuffles. +/// Handle lowering of 4-lane 64-bit integer shuffles. /// /// This routine is only called when we have AVX2 and thus a reasonable /// instruction set for v4i64 shuffling.. @@ -13709,7 +13709,7 @@ static SDValue lowerV4I64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, Mask, DAG); } -/// \brief Handle lowering of 8-lane 32-bit floating point shuffles. +/// Handle lowering of 8-lane 32-bit floating point shuffles. /// /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2 /// isn't available. @@ -13808,7 +13808,7 @@ static SDValue lowerV8F32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG); } -/// \brief Handle lowering of 8-lane 32-bit integer shuffles. +/// Handle lowering of 8-lane 32-bit integer shuffles. /// /// This routine is only called when we have AVX2 and thus a reasonable /// instruction set for v8i32 shuffling.. @@ -13921,7 +13921,7 @@ static SDValue lowerV8I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, Mask, DAG); } -/// \brief Handle lowering of 16-lane 16-bit integer shuffles. +/// Handle lowering of 16-lane 16-bit integer shuffles. /// /// This routine is only called when we have AVX2 and thus a reasonable /// instruction set for v16i16 shuffling.. @@ -14012,7 +14012,7 @@ static SDValue lowerV16I16VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG); } -/// \brief Handle lowering of 32-lane 8-bit integer shuffles. +/// Handle lowering of 32-lane 8-bit integer shuffles. /// /// This routine is only called when we have AVX2 and thus a reasonable /// instruction set for v32i8 shuffling.. @@ -14092,7 +14092,7 @@ static SDValue lowerV32I8VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG); } -/// \brief High-level routine to lower various 256-bit x86 vector shuffles. +/// High-level routine to lower various 256-bit x86 vector shuffles. /// /// This routine either breaks down the specific type of a 256-bit x86 vector /// shuffle or splits it into two 128-bit shuffles and fuses the results back @@ -14162,7 +14162,7 @@ static SDValue lower256BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, } } -/// \brief Try to lower a vector shuffle as a 128-bit shuffles. +/// Try to lower a vector shuffle as a 128-bit shuffles. static SDValue lowerV4X128VectorShuffle(const SDLoc &DL, MVT VT, ArrayRef<int> Mask, const APInt &Zeroable, @@ -14263,7 +14263,7 @@ static SDValue lowerV4X128VectorShuffle(const SDLoc &DL, MVT VT, DAG.getConstant(PermMask, DL, MVT::i8)); } -/// \brief Handle lowering of 8-lane 64-bit floating point shuffles. +/// Handle lowering of 8-lane 64-bit floating point shuffles. static SDValue lowerV8F64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, const APInt &Zeroable, SDValue V1, SDValue V2, @@ -14320,7 +14320,7 @@ static SDValue lowerV8F64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG); } -/// \brief Handle lowering of 16-lane 32-bit floating point shuffles. +/// Handle lowering of 16-lane 32-bit floating point shuffles. static SDValue lowerV16F32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, const APInt &Zeroable, SDValue V1, SDValue V2, @@ -14375,7 +14375,7 @@ static SDValue lowerV16F32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG); } -/// \brief Handle lowering of 8-lane 64-bit integer shuffles. +/// Handle lowering of 8-lane 64-bit integer shuffles. static SDValue lowerV8I64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, const APInt &Zeroable, SDValue V1, SDValue V2, @@ -14441,7 +14441,7 @@ static SDValue lowerV8I64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG); } -/// \brief Handle lowering of 16-lane 32-bit integer shuffles. +/// Handle lowering of 16-lane 32-bit integer shuffles. static SDValue lowerV16I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, const APInt &Zeroable, SDValue V1, SDValue V2, @@ -14512,7 +14512,7 @@ static SDValue lowerV16I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG); } -/// \brief Handle lowering of 32-lane 16-bit integer shuffles. +/// Handle lowering of 32-lane 16-bit integer shuffles. static SDValue lowerV32I16VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, const APInt &Zeroable, SDValue V1, SDValue V2, @@ -14567,7 +14567,7 @@ static SDValue lowerV32I16VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG); } -/// \brief Handle lowering of 64-lane 8-bit integer shuffles. +/// Handle lowering of 64-lane 8-bit integer shuffles. static SDValue lowerV64I8VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, const APInt &Zeroable, SDValue V1, SDValue V2, @@ -14622,7 +14622,7 @@ static SDValue lowerV64I8VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG); } -/// \brief High-level routine to lower various 512-bit x86 vector shuffles. +/// High-level routine to lower various 512-bit x86 vector shuffles. /// /// This routine either breaks down the specific type of a 512-bit x86 vector /// shuffle or splits it into two 256-bit shuffles and fuses the results back @@ -14825,7 +14825,7 @@ static bool canonicalizeShuffleMaskWithCommute(ArrayRef<int> Mask) { return false; } -/// \brief Top-level lowering for x86 vector shuffles. +/// Top-level lowering for x86 vector shuffles. /// /// This handles decomposition, canonicalization, and lowering of all x86 /// vector shuffles. Most of the specific lowering strategies are encapsulated @@ -14928,7 +14928,7 @@ static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget &Subtarget, llvm_unreachable("Unimplemented!"); } -/// \brief Try to lower a VSELECT instruction to a vector shuffle. +/// Try to lower a VSELECT instruction to a vector shuffle. static SDValue lowerVSELECTtoVectorShuffle(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG) { @@ -17430,7 +17430,7 @@ static SDValue LowerVectorAllZeroTest(SDValue Op, ISD::CondCode CC, return getSETCC(CC == ISD::SETEQ ? X86::COND_E : X86::COND_NE, Res, DL, DAG); } -/// \brief return true if \c Op has a use that doesn't just read flags. +/// return true if \c Op has a use that doesn't just read flags. static bool hasNonFlagsUse(SDValue Op) { for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE; ++UI) { @@ -18070,7 +18070,7 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) { DAG.getConstant(SSECC, dl, MVT::i8)); } -/// \brief Try to turn a VSETULT into a VSETULE by modifying its second +/// Try to turn a VSETULT into a VSETULE by modifying its second /// operand \p Op1. If non-trivial (for example because it's not constant) /// return an empty value. static SDValue ChangeVSETULTtoVSETULE(const SDLoc &dl, SDValue Op1, @@ -20059,7 +20059,7 @@ static SDValue getTargetVShiftNode(unsigned Opc, const SDLoc &dl, MVT VT, return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); } -/// \brief Return Mask with the necessary casting or extending +/// Return Mask with the necessary casting or extending /// for \p Mask according to \p MaskVT when lowering masking intrinsics static SDValue getMaskNode(SDValue Mask, MVT MaskVT, const X86Subtarget &Subtarget, SelectionDAG &DAG, @@ -20101,7 +20101,7 @@ static SDValue getMaskNode(SDValue Mask, MVT MaskVT, } } -/// \brief Return (and \p Op, \p Mask) for compare instructions or +/// Return (and \p Op, \p Mask) for compare instructions or /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the /// necessary casting or extending for \p Mask when lowering masking intrinsics static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask, @@ -20142,7 +20142,7 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask, return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc); } -/// \brief Creates an SDNode for a predicated scalar operation. +/// Creates an SDNode for a predicated scalar operation. /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc). /// The mask is coming as MVT::i8 and it should be transformed /// to MVT::v1i1 while lowering masking intrinsics. @@ -22086,7 +22086,7 @@ static SDValue Lower512IntUnary(SDValue Op, SelectionDAG &DAG) { return LowerVectorIntUnary(Op, DAG); } -/// \brief Lower a vector CTLZ using native supported vector CTLZ instruction. +/// Lower a vector CTLZ using native supported vector CTLZ instruction. // // i8/i16 vector implemented using dword LZCNT vector instruction // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal, @@ -28972,7 +28972,7 @@ static bool matchBinaryPermuteVectorShuffle( return false; } -/// \brief Combine an arbitrary chain of shuffles into a single instruction if +/// Combine an arbitrary chain of shuffles into a single instruction if /// possible. /// /// This is the leaf of the recursive combine below. When we have found some @@ -29498,7 +29498,7 @@ static SDValue combineX86ShufflesConstants(const SmallVectorImpl<SDValue> &Ops, return DAG.getBitcast(VT, CstOp); } -/// \brief Fully generic combining of x86 shuffle instructions. +/// Fully generic combining of x86 shuffle instructions. /// /// This should be the last combine run over the x86 shuffle instructions. Once /// they have been fully optimized, this will recursively consider all chains @@ -29730,7 +29730,7 @@ static SDValue combineX86ShufflesRecursively( Subtarget); } -/// \brief Get the PSHUF-style mask from PSHUF node. +/// Get the PSHUF-style mask from PSHUF node. /// /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4 /// PSHUF-style masks that can be reused with such instructions. @@ -29773,7 +29773,7 @@ static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) { } } -/// \brief Search for a combinable shuffle across a chain ending in pshufd. +/// Search for a combinable shuffle across a chain ending in pshufd. /// /// We walk up the chain and look for a combinable shuffle, skipping over /// shuffles that we could hoist this shuffle's transformation past without @@ -29906,7 +29906,7 @@ combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask, return V; } -/// \brief Search for a combinable shuffle across a chain ending in pshuflw or +/// Search for a combinable shuffle across a chain ending in pshuflw or /// pshufhw. /// /// We walk up the chain, skipping shuffles of the other half and looking @@ -29974,7 +29974,7 @@ static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask, return true; } -/// \brief Try to combine x86 target specific shuffles. +/// Try to combine x86 target specific shuffles. static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { @@ -30382,7 +30382,7 @@ static bool isAddSubOrSubAdd(SDNode *N, const X86Subtarget &Subtarget, return true; } -/// \brief Try to combine a shuffle into a target-specific add-sub or +/// Try to combine a shuffle into a target-specific add-sub or /// mul-add-sub node. static SDValue combineShuffleToAddSubOrFMAddSub(SDNode *N, const X86Subtarget &Subtarget, |
