diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86CallLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86CallLowering.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86CallLowering.cpp b/llvm/lib/Target/X86/X86CallLowering.cpp index 3f5b007f23e..6403d968941 100644 --- a/llvm/lib/Target/X86/X86CallLowering.cpp +++ b/llvm/lib/Target/X86/X86CallLowering.cpp @@ -61,6 +61,7 @@ bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg, SmallVector<EVT, 4> SplitVTs; SmallVector<uint64_t, 4> Offsets; ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0); + assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet"); if (OrigArg.Ty->isVoidTy()) return true; @@ -70,7 +71,7 @@ bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg, if (NumParts == 1) { // replace the original type ( pointer -> GPR ). - SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context), + SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context), OrigArg.Flags, OrigArg.IsFixed); return true; } @@ -85,7 +86,7 @@ bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg, ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)), PartTy, OrigArg.Flags}; SplitArgs.push_back(Info); - SplitRegs.push_back(Info.Reg); + SplitRegs.push_back(Info.Regs[0]); } PerformArgSplit(SplitRegs); @@ -408,9 +409,10 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (OrigArg.Flags.isByVal()) return false; + assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet"); if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI, [&](ArrayRef<Register> Regs) { - MIRBuilder.buildUnmerge(Regs, OrigArg.Reg); + MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]); })) return false; } @@ -450,7 +452,9 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, // symmetry with the arguments, the physical register must be an // implicit-define of the call instruction. - if (OrigRet.Reg) { + if (!OrigRet.Ty->isVoidTy()) { + assert(OrigRet.Regs.size() == 1 && "Can't handle multple regs yet"); + SplitArgs.clear(); SmallVector<Register, 8> NewRegs; @@ -465,7 +469,7 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, return false; if (!NewRegs.empty()) - MIRBuilder.buildMerge(OrigRet.Reg, NewRegs); + MIRBuilder.buildMerge(OrigRet.Regs[0], NewRegs); } CallSeqStart.addImm(Handler.getStackSize()) |
