diff options
Diffstat (limited to 'llvm/lib/Target/X86/MCTargetDesc')
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h | 10 |
2 files changed, 13 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index 239db2a74b2..717e2f44f56 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -843,10 +843,12 @@ public: } // end anonymous namespace MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, + const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, - const Triple &TheTriple, - StringRef CPU, const MCTargetOptions &Options) { + const Triple &TheTriple = STI.getTargetTriple(); + StringRef CPU = STI.getCPU(); + llvm::errs() << "create x86-32 backend with CPU: " << CPU << "\n"; if (TheTriple.isOSBinFormatMachO()) return new DarwinX86_32AsmBackend(T, MRI, CPU); @@ -862,10 +864,11 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, } MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, + const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, - const Triple &TheTriple, - StringRef CPU, const MCTargetOptions &Options) { + const Triple &TheTriple = STI.getTargetTriple(); + StringRef CPU = STI.getCPU(); if (TheTriple.isOSBinFormatMachO()) { MachO::CPUSubTypeX86 CS = StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h index c5859b600ad..d758c0588cb 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -70,11 +70,13 @@ MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, +MCAsmBackend *createX86_32AsmBackend(const Target &T, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, const MCTargetOptions &Options); -MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, +MCAsmBackend *createX86_64AsmBackend(const Target &T, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, const MCTargetOptions &Options); /// Implements X86-only directives for assembly emission. |
