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-rw-r--r--llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp21
1 files changed, 0 insertions, 21 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index e3c427f8ced..0837b69d3f9 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -877,27 +877,6 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
}
- // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
- // synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the
- // other operand order, swap them.
- if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"||
- Name == "xchg")
- if (Operands.size() == 3 &&
- static_cast<X86Operand*>(Operands[1])->isMem() &&
- static_cast<X86Operand*>(Operands[2])->isReg()) {
- std::swap(Operands[1], Operands[2]);
- }
-
- // The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
- // synonyms. Our tables only have the "<mem>, <reg>" form, so if we see the
- // other operand order, swap them.
- if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"||
- Name == "test")
- if (Operands.size() == 3 &&
- static_cast<X86Operand*>(Operands[1])->isReg() &&
- static_cast<X86Operand*>(Operands[2])->isMem()) {
- std::swap(Operands[1], Operands[2]);
- }
// The assembler accepts these instructions with no operand as a synonym for
// an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
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