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-rw-r--r--llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp33
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 576629fce89..e8e4b839d3b 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2712,6 +2712,39 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
"should be distinct");
break;
}
+ case X86::V4FMADDPSrm:
+ case X86::V4FMADDPSrmk:
+ case X86::V4FMADDPSrmkz:
+ case X86::V4FMADDSSrm:
+ case X86::V4FMADDSSrmk:
+ case X86::V4FMADDSSrmkz:
+ case X86::V4FNMADDPSrm:
+ case X86::V4FNMADDPSrmk:
+ case X86::V4FNMADDPSrmkz:
+ case X86::V4FNMADDSSrm:
+ case X86::V4FNMADDSSrmk:
+ case X86::V4FNMADDSSrmkz:
+ case X86::VP4DPWSSDSrm:
+ case X86::VP4DPWSSDSrmk:
+ case X86::VP4DPWSSDSrmkz:
+ case X86::VP4DPWSSDrm:
+ case X86::VP4DPWSSDrmk:
+ case X86::VP4DPWSSDrmkz: {
+ unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
+ X86::AddrNumOperands - 1).getReg();
+ unsigned Src2Enc = MRI->getEncodingValue(Src2);
+ if (Src2Enc % 4 != 0) {
+ StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2);
+ unsigned GroupStart = (Src2Enc / 4) * 4;
+ unsigned GroupEnd = GroupStart + 3;
+ return Warning(Ops[Ops.size()-2]->getStartLoc(),
+ "source register implicitly denotes '" +
+ RegName.take_front(3) + Twine(GroupStart) + "' to '" +
+ RegName.take_front(3) + Twine(GroupEnd) +
+ "' source group");
+ }
+ break;
+ }
}
return false;
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