diff options
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 45 |
1 files changed, 44 insertions, 1 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index afde9ec63cb..459e00a25d6 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -18,13 +18,28 @@ def ImmI#SIZE : ImmLeaf<i32, "return (Imm & ((1UL << "#SIZE#") - 1)) == Imm;">; foreach SIZE = [2, 4, 8, 16, 32] in def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; -// const vectors multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, [(set V128:$dst, (vec_t pat))], "v128.const\t$dst, "#args, "v128.const\t"#args, 0>; } +multiclass SIMDLoad<ValueType vec_t> { + let mayLoad = 1 in + defm LOAD_#vec_t : + SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr), + (outs), (ins P2Align:$align, offset32_op:$off), [], + "v128.load\t$dst, ${off}(${addr})$align", + "v128.load\t$off$align", 1>; +} +multiclass SIMDStore<ValueType vec_t> { + let mayStore = 1 in + defm STORE_#vec_t : + SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec), + (outs), (ins P2Align:$align, offset32_op:$off), [], + "v128.store\t${off}(${addr})$align, $vec", + "v128.store\t$off$align", 2>; +} multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t, WebAssemblyRegClass reg_t, bits<32> simdop, string suffix = "", SDNode extract = vector_extract> { @@ -177,6 +192,11 @@ defm "" : ConstVec<v2f64, (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), "$i0, $i1">; +foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { +defm "" : SIMDLoad<vec_t>; +defm "" : SIMDStore<vec_t>; +} + defm "" : ExtractLaneExtended<"_s", 9>; defm "" : ExtractLaneExtended<"_u", 10>; defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>; @@ -222,6 +242,29 @@ defm "" : SIMDNot<v2i64, splat2, i64>; } // Defs = [ARGUMENTS] +// Def load and store patterns from WebAssemblyInstrMemory.td for vector types +foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { + +def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>; +def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>; +def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>; +def : LoadPatGlobalAddr<vec_t, load, !cast<NI>("LOAD_"#vec_t)>; +def : LoadPatExternalSym<vec_t, load, !cast<NI>("LOAD_"#vec_t)>; +def : LoadPatOffsetOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>; +def : LoadPatGlobalAddrOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>; +def : LoadPatExternSymOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>; + +def : StorePatNoOffset<vec_t, store, !cast<NI>("STORE_"#vec_t)>; +def : StorePatImmOff<vec_t, store, regPlusImm, !cast<NI>("STORE_"#vec_t)>; +def : StorePatImmOff<vec_t, store, or_is_add, !cast<NI>("STORE_"#vec_t)>; +def : StorePatGlobalAddr<vec_t, store, !cast<NI>("STORE_"#vec_t)>; +def : StorePatExternalSym<vec_t, store, !cast<NI>("STORE_"#vec_t)>; +def : StorePatOffsetOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>; +def : StorePatGlobalAddrOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>; +def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>; + +} + // follow convention of making implicit expansions unsigned def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))), (EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>; |
