diff options
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZShortenInst.cpp')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZShortenInst.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp index 083718518f2..65bd3f0a214 100644 --- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp +++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp @@ -78,12 +78,14 @@ bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned Reg = MI.getOperand(0).getReg(); // The new opcode will clear the other half of the GR64 reg, so // cancel if that is live. - unsigned thisSubRegIdx = (SystemZ::GRH32BitRegClass.contains(Reg) ? - SystemZ::subreg_h32 : SystemZ::subreg_l32); - unsigned otherSubRegIdx = (thisSubRegIdx == SystemZ::subreg_l32 ? - SystemZ::subreg_h32 : SystemZ::subreg_l32); - unsigned GR64BitReg = TRI->getMatchingSuperReg(Reg, thisSubRegIdx, - &SystemZ::GR64BitRegClass); + unsigned thisSubRegIdx = + (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32 + : SystemZ::subreg_l32); + unsigned otherSubRegIdx = + (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32 + : SystemZ::subreg_l32); + unsigned GR64BitReg = + TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass); unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); if (LiveRegs.contains(OtherReg)) return false; @@ -139,8 +141,7 @@ bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { // Calls shortenOn001 if CCLive is false. CC def operand is added in // case of success. -bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, - unsigned Opcode) { +bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) { MachineInstrBuilder(*MI.getParent()->getParent(), &MI) .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); |
