1 files changed, 67 insertions, 32 deletions

diff --git a/llvm/lib/Target/SystemZ/SystemZSchedule.td b/llvm/lib/Target/SystemZ/SystemZSchedule.td
index 8dba89f70a4..7cdb774cd4a 100644
--- a/llvm/lib/Target/SystemZ/SystemZSchedule.td
+++ b/llvm/lib/Target/SystemZ/SystemZSchedule.td
@@ -8,72 +8,107 @@
 //===----------------------------------------------------------------------===//
 
 // Scheduler resources
-// Resources ending with a '2' use that resource for 2 cycles. An instruction
-// using two such resources use the mapped unit for 4 cycles, and 2 is added
-// to the total number of uops of the sched class.
 
-// These three resources are used to express decoder grouping rules.
-// The number of decoder slots needed by an instructions is normally
-// one. For a cracked instruction (BeginGroup && !EndGroup) it is
-// two. Expanded instructions (BeginGroup && EndGroup) group alone.
+// These resources are used to express decoder grouping rules.  The number of
+// decoder slots needed by an instructions is normally one, but there are
+// exceptions.
+def NormalGr   : SchedWrite;
+def Cracked    : SchedWrite;
 def GroupAlone : SchedWrite;
 def BeginGroup : SchedWrite;
 def EndGroup   : SchedWrite;
 
-// Latencies, to make code a bit neater. If more than one resource is
-// used for an instruction, the greatest latency (not the sum) will be
-// output by Tablegen. Therefore, in such cases one of these resources
-// is needed.
-def Lat2 : SchedWrite;
-def Lat3 : SchedWrite;
-def Lat4 : SchedWrite;
-def Lat5 : SchedWrite;
-def Lat6 : SchedWrite;
-def Lat7 : SchedWrite;
-def Lat8 : SchedWrite;
-def Lat9 : SchedWrite;
-def Lat10 : SchedWrite;
-def Lat11 : SchedWrite;
-def Lat12 : SchedWrite;
-def Lat15 : SchedWrite;
-def Lat20 : SchedWrite;
-def Lat30 : SchedWrite;
+// A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
+def LSULatency : SchedWrite;
 
-// Fixed-point
+// Operand WriteLatencies.
+def WLat1 : SchedWrite;
+def WLat2 : SchedWrite;
+def WLat3 : SchedWrite;
+def WLat4 : SchedWrite;
+def WLat5 : SchedWrite;
+def WLat6 : SchedWrite;
+def WLat7 : SchedWrite;
+def WLat8 : SchedWrite;
+def WLat9 : SchedWrite;
+def WLat10 : SchedWrite;
+def WLat11 : SchedWrite;
+def WLat12 : SchedWrite;
+def WLat15 : SchedWrite;
+def WLat16 : SchedWrite;
+def WLat20 : SchedWrite;
+def WLat26 : SchedWrite;
+def WLat30 : SchedWrite;
+
+def WLat1LSU : WriteSequence<[WLat1, LSULatency]>;
+def WLat2LSU : WriteSequence<[WLat2, LSULatency]>;
+def WLat3LSU : WriteSequence<[WLat3, LSULatency]>;
+def WLat4LSU : WriteSequence<[WLat4, LSULatency]>;
+def WLat6LSU : WriteSequence<[WLat6, LSULatency]>;
+def WLat5LSU : WriteSequence<[WLat5, LSULatency]>;
+def WLat7LSU : WriteSequence<[WLat7, LSULatency]>;
+def WLat8LSU : WriteSequence<[WLat8, LSULatency]>;
+def WLat11LSU : WriteSequence<[WLat11, LSULatency]>;
+def WLat16LSU : WriteSequence<[WLat16, LSULatency]>;
+
+// ReadAdvances, used for the register operand next to a memory operand,
+// modelling that the register operand is needed later than the address
+// operands.
+def RegReadAdv : SchedRead;
+
+// Fixed-point units
 def FXa         : SchedWrite;
 def FXa2        : SchedWrite;
+def FXa3        : SchedWrite;
+def FXa4        : SchedWrite;
 def FXb         : SchedWrite;
+def FXb2        : SchedWrite;
+def FXb3        : SchedWrite;
+def FXb4        : SchedWrite;
+def FXb5        : SchedWrite;
 def FXU         : SchedWrite;
+def FXU2        : SchedWrite;
+def FXU3        : SchedWrite;
+def FXU4        : SchedWrite;
+def FXU5        : SchedWrite;
+def FXU6        : SchedWrite;
 
 // Load/store unit
 def LSU         : SchedWrite;
-
-// Model a return without latency, otherwise if-converter will model
-// extra cost and abort (currently there is an assert that checks that
-// all instructions have at least one uop).
-def LSU_lat1    : SchedWrite;
+def LSU2        : SchedWrite;
+def LSU3        : SchedWrite;
+def LSU4        : SchedWrite;
+def LSU5        : SchedWrite;
 
 // Floating point unit (zEC12 and earlier)
 def FPU  : SchedWrite;
 def FPU2 : SchedWrite;
+def FPU4 : SchedWrite;
 def DFU  : SchedWrite;
 def DFU2 : SchedWrite;
+def DFU4 : SchedWrite;
 
 // Vector sub units (z13 and later)
 def VecBF     : SchedWrite;
 def VecBF2    : SchedWrite;
+def VecBF4    : SchedWrite;
 def VecDF     : SchedWrite;
 def VecDF2    : SchedWrite;
+def VecDF4    : SchedWrite;
 def VecDFX    : SchedWrite;
 def VecDFX2   : SchedWrite;
+def VecDFX4   : SchedWrite;
 def VecFPd    : SchedWrite; // Blocking BFP div/sqrt unit.
 def VecMul    : SchedWrite;
 def VecStr    : SchedWrite;
 def VecXsPm   : SchedWrite;
+def VecXsPm2  : SchedWrite;
 
 // Virtual branching unit
-def VBU         : SchedWrite;
+def VBU       : SchedWrite;
 
+// Millicode
+def MCD       : SchedWrite;
 
 include "SystemZScheduleZ14.td"
 include "SystemZScheduleZ13.td"