diff options
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index a8357a13538..11d13062a9d 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -107,19 +107,19 @@ namespace { /// getI8Imm - Return a target constant with the specified value, of type /// i8. inline SDValue getI8Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, EVT::i8); + return CurDAG->getTargetConstant(Imm, MVT::i8); } /// getI16Imm - Return a target constant with the specified value, of type /// i16. inline SDValue getI16Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, EVT::i16); + return CurDAG->getTargetConstant(Imm, MVT::i16); } /// getI32Imm - Return a target constant with the specified value, of type /// i32. inline SDValue getI32Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, EVT::i32); + return CurDAG->getTargetConstant(Imm, MVT::i32); } // Include the pieces autogenerated from the target description. @@ -353,7 +353,7 @@ void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM, Base = AM.Base.Reg; else Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()); - Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i64); + Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64); } void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM, @@ -650,16 +650,16 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { EVT ResVT; bool is32Bit = false; - switch (NVT.getSimpleVT()) { + switch (NVT.getSimpleVT().SimpleTy) { default: assert(0 && "Unsupported VT!"); - case EVT::i32: + case MVT::i32: Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; - ResVT = EVT::v2i64; + ResVT = MVT::v2i64; is32Bit = true; break; - case EVT::i64: + case MVT::i64: Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m; - ResVT = EVT::v2i64; + ResVT = MVT::v2i64; break; } @@ -669,7 +669,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { // Prepare the dividend SDNode *Dividend; if (is32Bit) - Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, EVT::i64, N0); + Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0); else Dividend = N0.getNode(); @@ -679,7 +679,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { Dividend = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, SDValue(Tmp, 0), SDValue(Dividend, 0), - CurDAG->getTargetConstant(subreg_odd, EVT::i32)); + CurDAG->getTargetConstant(subreg_odd, MVT::i32)); SDNode *Result; SDValue DivVal = SDValue(Dividend, 0); @@ -699,7 +699,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - EVT::i32)); + MVT::i32)); ReplaceUses(Op.getValue(0), SDValue(Div, 0)); #ifndef NDEBUG @@ -716,7 +716,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - EVT::i32)); + MVT::i32)); ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); #ifndef NDEBUG @@ -739,18 +739,18 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { EVT ResVT; bool is32Bit = false; - switch (NVT.getSimpleVT()) { + switch (NVT.getSimpleVT().SimpleTy) { default: assert(0 && "Unsupported VT!"); - case EVT::i32: + case MVT::i32: Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; ClrOpc = SystemZ::MOV64Pr0_even; - ResVT = EVT::v2i32; + ResVT = MVT::v2i32; is32Bit = true; break; - case EVT::i64: + case MVT::i64: Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; ClrOpc = SystemZ::MOV128r0_even; - ResVT = EVT::v2i64; + ResVT = MVT::v2i64; break; } @@ -768,7 +768,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { Dividend = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, SDValue(Tmp, 0), SDValue(Dividend, 0), - CurDAG->getTargetConstant(SubRegIdx, EVT::i32)); + CurDAG->getTargetConstant(SubRegIdx, MVT::i32)); } // Zero out even subreg @@ -793,7 +793,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - EVT::i32)); + MVT::i32)); ReplaceUses(Op.getValue(0), SDValue(Div, 0)); #ifndef NDEBUG DOUT << std::string(Indent-2, ' ') << "=> "; @@ -809,7 +809,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - EVT::i32)); + MVT::i32)); ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); #ifndef NDEBUG DOUT << std::string(Indent-2, ' ') << "=> "; |
