diff options
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 6979a176232..d43cd9e3127 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -22,11 +22,13 @@ extern "C" void LLVMInitializeSparcTarget() { // Register the target. RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); + RegisterTargetMachine<SparcelTargetMachine> Z(TheSparcelTarget); } -static std::string computeDataLayout(bool is64Bit) { - // Sparc is big endian. - std::string Ret = "E-m:e"; +static std::string computeDataLayout(const Triple &T, bool is64Bit) { + // Sparc is typically big endian, but some are little. + std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E"; + Ret += "-m:e"; // Some ABIs have 32bit pointers. if (!is64Bit) @@ -57,8 +59,8 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) - : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM, - CM, OL), + : LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS, + Options, RM, CM, OL), TLOF(make_unique<SparcELFTargetObjectFile>()), Subtarget(TT, CPU, FS, *this, is64bit) { initAsmInfo(); @@ -116,12 +118,18 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, void SparcV9TargetMachine::anchor() { } -SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, - StringRef TT, StringRef CPU, - StringRef FS, +SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, - CodeModel::Model CM, + Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { -} + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + +void SparcelTargetMachine::anchor() {} + +SparcelTargetMachine::SparcelTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} |
