diff options
Diffstat (limited to 'llvm/lib/Target/RISCV')
| -rw-r--r-- | llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 69 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp | 101 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.h | 29 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 65 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrFormats.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 24 |
9 files changed, 49 insertions, 266 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 7f0433410d0..521d72b546d 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -9,7 +9,6 @@ #include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVMCExpr.h" -#include "MCTargetDesc/RISCVMCPseudoExpansion.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -23,11 +22,8 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Casting.h" -#include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetRegistry.h" -#include <limits> - using namespace llvm; // Include the auto-generated portion of the compress emitter. @@ -45,7 +41,7 @@ class RISCVAsmParser : public MCTargetAsmParser { unsigned Kind) override; bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo, - int64_t Lower, int64_t Upper, Twine Msg); + int Lower, int Upper, Twine Msg); bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -59,12 +55,6 @@ class RISCVAsmParser : public MCTargetAsmParser { bool ParseDirective(AsmToken DirectiveID) override; - /// Helper for emitting MC instructions that have been successfully matched - /// by MatchAndEmitInstruction. Modifications to the emitted instructions, - /// like the expansion of pseudo instructions (e.g., "li"), can be performed - /// in this method. - bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out); - // Auto-generated instruction matching functions #define GET_ASSEMBLER_HEADER #include "RISCVGenAsmMatcher.inc" @@ -220,18 +210,6 @@ public: return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid; } - bool isImmXLen() const { - int64_t Imm; - RISCVMCExpr::VariantKind VK; - if (!isImm()) - return false; - bool IsConstantImm = evaluateConstantImm(Imm, VK); - // Given only Imm, ensuring that the actually specified constant is either - // a signed or unsigned 64-bit number is unfortunately impossible. - bool IsInRange = isRV64() ? true : isInt<32>(Imm) || isUInt<32>(Imm); - return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None; - } - bool isUImmLog2XLen() const { int64_t Imm; RISCVMCExpr::VariantKind VK; @@ -605,7 +583,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, } bool RISCVAsmParser::generateImmOutOfRangeError( - OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper, + OperandVector &Operands, uint64_t ErrorInfo, int Lower, int Upper, Twine Msg = "immediate must be an integer in the range") { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]"); @@ -621,8 +599,14 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { default: break; - case Match_Success: - return processInstruction(Inst, IDLoc, Out); + case Match_Success: { + MCInst CInst; + bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext()); + CInst.setLoc(IDLoc); + Inst.setLoc(IDLoc); + Out.EmitInstruction((Res ? CInst : Inst), getSTI()); + return false; + } case Match_MissingFeature: return Error(IDLoc, "instruction use requires an option to be enabled"); case Match_MnemonicFail: @@ -639,14 +623,6 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } return Error(ErrorLoc, "invalid operand for instruction"); } - case Match_InvalidImmXLen: - if (isRV64()) { - SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); - return Error(ErrorLoc, "operand must be a constant 64-bit integer"); - } - return generateImmOutOfRangeError(Operands, ErrorInfo, - std::numeric_limits<int32_t>::min(), - std::numeric_limits<uint32_t>::max()); case Match_InvalidUImmLog2XLen: if (isRV64()) return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1); @@ -991,31 +967,6 @@ bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr, return Kind != RISCVMCExpr::VK_RISCV_Invalid; } -bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, - MCStreamer &Out) { - Inst.setLoc(IDLoc); - - switch (Inst.getOpcode()) { - case RISCV::PseudoLI: { - auto Reg = Inst.getOperand(0).getReg(); - int64_t Imm = Inst.getOperand(1).getImm(); - // On RV32 the immediate here can either be a signed or an unsigned - // 32-bit number. Sign extension has to be performed to ensure that Imm - // represents the expected signed 64-bit number. - if (!isRV64()) - Imm = SignExtend64<32>(Imm); - emitRISCVLoadImm(Reg, Imm, Out, STI); - return false; - } - } - - MCInst CInst; - bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext()); - CInst.setLoc(IDLoc); - Out.EmitInstruction((Res ? CInst : Inst), getSTI()); - return false; -} - bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { return true; } extern "C" void LLVMInitializeRISCVAsmParser() { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt index 2ea149a388d..d9f4188aa75 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt @@ -4,7 +4,6 @@ add_llvm_library(LLVMRISCVDesc RISCVMCAsmInfo.cpp RISCVMCCodeEmitter.cpp RISCVMCExpr.cpp - RISCVMCPseudoExpansion.cpp RISCVMCTargetDesc.cpp RISCVTargetStreamer.cpp RISCVELFStreamer.cpp diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp deleted file mode 100644 index 406c4c20fe9..00000000000 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp +++ /dev/null @@ -1,101 +0,0 @@ -//===-- RISCVMCPseudoExpansion.cpp - RISCV MC Pseudo Expansion ------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -/// -/// This file provides helpers to expand pseudo MC instructions that are usable -/// in the AsmParser and the AsmPrinter. -/// -//===----------------------------------------------------------------------===// - -#include "RISCVMCPseudoExpansion.h" -#include "RISCVMCTargetDesc.h" -#include "llvm/MC/MCInstBuilder.h" -#include "llvm/MC/MCStreamer.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/MathExtras.h" - -#include <cassert> - -using namespace llvm; - -void llvm::emitRISCVLoadImm(unsigned DestReg, int64_t Value, MCStreamer &Out, - const MCSubtargetInfo *STI) { - if (isInt<32>(Value)) { - // Emits the MC instructions for loading a 32-bit constant into a register. - // - // Depending on the active bits in the immediate Value v, the following - // instruction sequences are emitted: - // - // v == 0 : ADDI(W) - // v[0,12) != 0 && v[12,32) == 0 : ADDI(W) - // v[0,12) == 0 && v[12,32) != 0 : LUI - // v[0,32) != 0 : LUI+ADDI(W) - // - int64_t Hi20 = ((Value + 0x800) >> 12) & 0xFFFFF; - int64_t Lo12 = SignExtend64<12>(Value); - unsigned SrcReg = RISCV::X0; - - if (Hi20) { - Out.EmitInstruction( - MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Hi20), *STI); - SrcReg = DestReg; - } - - if (Lo12 || Hi20 == 0) { - unsigned AddiOpcode = - STI->hasFeature(RISCV::Feature64Bit) ? RISCV::ADDIW : RISCV::ADDI; - Out.EmitInstruction( - MCInstBuilder(AddiOpcode).addReg(DestReg).addReg(SrcReg).addImm(Lo12), - *STI); - } - return; - } - assert(STI->hasFeature(RISCV::Feature64Bit) && - "Target must be 64-bit to support a >32-bit constant"); - - // In the worst case, for a full 64-bit constant, a sequence of 8 instructions - // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note - // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits - // while the following ADDI instructions contribute up to 12 bits each. - // - // On the first glance, implementing this seems to be possible by simply - // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left - // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the - // fact that ADDI performs a sign extended addition, doing it like that would - // only be possible when at most 11 bits of the ADDI instructions are used. - // Using all 12 bits of the ADDI instructions, like done by GAS, actually - // requires that the constant is processed starting with the least significant - // bit. - // - // In the following, constants are processed from LSB to MSB but instruction - // emission is performed from MSB to LSB by recursively calling - // emitRISCVLoadImm. In each recursion, first the lowest 12 bits are removed - // from the constant and the optimal shift amount, which can be greater than - // 12 bits if the constant is sparse, is determined. Then, the shifted - // remaining constant is processed recursively and gets emitted as soon as it - // fits into 32 bits. The emission of the shifts and additions is subsequently - // performed when the recursion returns. - // - int64_t Lo12 = SignExtend64<12>(Value); - int64_t Hi52 = (Value + 0x800) >> 12; - int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); - Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); - - emitRISCVLoadImm(DestReg, Hi52, Out, STI); - - Out.EmitInstruction(MCInstBuilder(RISCV::SLLI) - .addReg(DestReg) - .addReg(DestReg) - .addImm(ShiftAmount), - *STI); - - if (Lo12) - Out.EmitInstruction( - MCInstBuilder(RISCV::ADDI).addReg(DestReg).addReg(DestReg).addImm(Lo12), - *STI); -} diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.h deleted file mode 100644 index 0a577a9bc33..00000000000 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.h +++ /dev/null @@ -1,29 +0,0 @@ -//===-- RISCVMCPseudoExpansion.h - RISCV MC Pseudo Expansion ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -/// This file describes helpers to expand pseudo MC instructions that are usable -/// in the AsmParser and the AsmPrinter. -// -//===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCPSEUDOEXPANSION_H -#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCPSEUDOEXPANSION_H - -#include <cstdint> - -namespace llvm { - -class MCStreamer; -class MCSubtargetInfo; - -void emitRISCVLoadImm(unsigned DestReg, int64_t Value, MCStreamer &Out, - const MCSubtargetInfo *STI); - -} // namespace llvm - -#endif diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 820cbe1ed5d..bdf8e5d840b 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -15,7 +15,6 @@ #include "RISCV.h" #include "InstPrinter/RISCVInstPrinter.h" #include "MCTargetDesc/RISCVMCExpr.h" -#include "MCTargetDesc/RISCVMCPseudoExpansion.h" #include "RISCVTargetMachine.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineConstantPool.h" @@ -79,14 +78,6 @@ void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (emitPseudoExpansionLowering(*OutStreamer, MI)) return; - if (MI->getOpcode() == RISCV::PseudoLI) { - const MachineOperand &DstRegOp = MI->getOperand(0); - const MachineOperand &ImmOp = MI->getOperand(1); - emitRISCVLoadImm(DstRegOp.getReg(), ImmOp.getImm(), *OutStreamer, - &getSubtargetInfo()); - return; - } - MCInst TmpInst; LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this); EmitToStreamer(*OutStreamer, TmpInst); diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 8fdf18efb58..630439bb53c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -179,62 +179,41 @@ void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() { SDValue Base = N->getOperand(BaseOpIdx); - // If the base is an ADDI or PseudoLI, we can either merge it or at least - // sink the lowest 12 bits into the load/store. - if (!Base.isMachineOpcode() || (Base.getMachineOpcode() != RISCV::ADDI && - Base.getMachineOpcode() != RISCV::PseudoLI)) + // If the base is an ADDI, we can merge it in to the load/store. + if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI) continue; - SDValue ImmOperand; - SDValue Parent; - if (Base.getMachineOpcode() == RISCV::PseudoLI) { - ImmOperand = Base.getOperand(0); - auto Const = dyn_cast<ConstantSDNode>(ImmOperand); - if (!Const || (Const->getSExtValue() & 0xFFF) == 0) - continue; - - int64_t Hi52 = (Const->getSExtValue() + 0x800) & ~0xFFF; - SDValue HiVal = CurDAG->getTargetConstant(Hi52, SDLoc(ImmOperand), - ImmOperand.getValueType()); - Parent = - SDValue(CurDAG->getMachineNode(RISCV::PseudoLI, SDLoc(ImmOperand), - ImmOperand.getValueType(), HiVal), - 0); - - int64_t Lo12 = SignExtend64<12>(Const->getSExtValue()); - ImmOperand = CurDAG->getTargetConstant(Lo12, SDLoc(ImmOperand), - ImmOperand.getValueType()); + SDValue ImmOperand = Base.getOperand(1); + + if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) { + ImmOperand = CurDAG->getTargetConstant( + Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType()); + } else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) { + ImmOperand = CurDAG->getTargetGlobalAddress( + GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(), + GA->getOffset(), GA->getTargetFlags()); } else { - Parent = Base.getOperand(0); - ImmOperand = Base.getOperand(1); - - if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) { - ImmOperand = - CurDAG->getTargetConstant(Const->getSExtValue(), SDLoc(ImmOperand), - ImmOperand.getValueType()); - } else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) { - ImmOperand = CurDAG->getTargetGlobalAddress( - GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(), - GA->getOffset(), GA->getTargetFlags()); - } else { - continue; - } + continue; } - DEBUG(dbgs() << "Folding add-immediate or PseudoLI into mem-op:\nBase: "); - DEBUG(Base.dump(CurDAG)); + DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); + DEBUG(Base->dump(CurDAG)); DEBUG(dbgs() << "\nN: "); DEBUG(N->dump(CurDAG)); DEBUG(dbgs() << "\n"); // Modify the offset operand of the load/store. if (BaseOpIdx == 0) // Load - CurDAG->UpdateNodeOperands(N, Parent, ImmOperand, N->getOperand(2)); + CurDAG->UpdateNodeOperands(N, Base.getOperand(0), ImmOperand, + N->getOperand(2)); else // Store - CurDAG->UpdateNodeOperands(N, N->getOperand(0), Parent, ImmOperand, - N->getOperand(3)); + CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0), + ImmOperand, N->getOperand(3)); + + // The add-immediate may now be dead, in which case remove it. + if (Base.getNode()->use_empty()) + CurDAG->RemoveDeadNode(Base.getNode()); } - CurDAG->RemoveDeadNodes(); } // Remove redundant BuildPairF64+SplitF64 pairs. i.e. cases where an f64 is diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index 529e048045c..7479ffbc953 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -102,8 +102,8 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr, } // Pseudo instructions -class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = ""> - : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> { +class Pseudo<dag outs, dag ins, list<dag> pattern> + : RVInst<outs, ins, "", "", pattern, InstFormatPseudo> { let isPseudo = 1; let isCodeGenOnly = 1; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index cbbe07a27bf..91a0dfb233f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -112,8 +112,17 @@ void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB, MachineInstr::MIFlag Flag) const { assert(isInt<32>(Val) && "Can only materialize 32-bit constants"); - BuildMI(MBB, MBBI, DL, get(RISCV::PseudoLI), DstReg) - .addImm(Val) + // TODO: If the value can be materialized using only one instruction, only + // insert a single instruction. + + uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff; + uint64_t Lo12 = SignExtend64<12>(Val); + BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg) + .addImm(Hi20) + .setMIFlag(Flag); + BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) + .addReg(DstReg, RegState::Kill) + .addImm(Lo12) .setMIFlag(Flag); } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 56fb9f60927..1c429da7419 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -43,12 +43,6 @@ def SelectCC : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC, // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// -class ImmXLenAsmOperand<string prefix, string suffix = ""> : AsmOperandClass { - let Name = prefix # "ImmXLen" # suffix; - let RenderMethod = "addImmOperands"; - let DiagnosticType = !strconcat("Invalid", Name); -} - class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass { let Name = prefix # "Imm" # width # suffix; let RenderMethod = "addImmOperands"; @@ -160,9 +154,7 @@ def simm21_lsb0 : Operand<OtherVT> { } // A parameterized register class alternative to i32imm/i64imm from Target.td. -def ixlenimm : Operand<XLenVT> { - let ParserMatchClass = ImmXLenAsmOperand<"">; -} +def ixlenimm : Operand<XLenVT>; // Standalone (codegen-only) immleaf patterns. def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>; @@ -426,16 +418,7 @@ def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs), // TODO RV64I: sd def : InstAlias<"nop", (ADDI X0, X0, 0)>; - -// Note that a size of 8 is currently correct because only 32-bit immediates -// are emitted as PseudoLI during codegen. Emitting larger constants as -// PseudoLI is probably not the best idea anyway given that up to -// 8 32-bit instructions are needed to generate an arbitrary 64-bit immediate. -let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, - isCodeGenOnly = 0, isAsmParserOnly = 1 in -def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm:$imm), [], - "li", "$rd, $imm">; - +// TODO li def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>; def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>; def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>; @@ -538,7 +521,8 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ /// Immediates def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>; -def : Pat<(simm32:$imm), (PseudoLI imm:$imm)>; +// TODO: Add a pattern for immediates with all zeroes in the lower 12 bits. +def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>; /// Simple arithmetic operations |
