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-rw-r--r--llvm/lib/Target/RISCV/RISCVInstrInfo.td6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 7dedc0ffcc1..71e058f1958 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -757,6 +757,12 @@ def : Pat<(atomic_fence (i32 6), (imm)), (FENCE_TSO)>;
// fence seq_cst -> fence rw, rw
def : Pat<(atomic_fence (i32 7), (imm)), (FENCE 0b11, 0b11)>;
+// Lowering for atomic load and store is defined in RISCVInstrInfoA.td.
+// Although these are lowered to fence+load/store instructions defined in the
+// base RV32I/RV64I ISA, this lowering is only used when the A extension is
+// present. This is necessary as it isn't valid to mix __atomic_* libcalls
+// with inline atomic operations for the same object.
+
/// Other pseudo-instructions
// Pessimistically assume the stack pointer will be clobbered
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