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-rw-r--r--llvm/lib/Target/RISCV/RISCVISelLowering.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9f0069878d8..b98f0575caa 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -137,6 +137,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BlockAddress, XLenVT, Custom);
setOperationAction(ISD::ConstantPool, XLenVT, Custom);
+ // Atomic operations aren't suported in the base RV32I ISA.
+ setMaxAtomicSizeInBitsSupported(0);
+
setBooleanContents(ZeroOrOneBooleanContent);
// Function alignments (log2).
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