diff options
Diffstat (limited to 'llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index 78776c11d75..65f3eb5d99a 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// #include "AMDGPU.h" +#include "SIDefines.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" #include "MCTargetDesc/AMDGPUFixupKinds.h" @@ -84,6 +85,15 @@ MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const { + // FIXME: We need a better way to figure out which operands can be immediate + // values + // + // Some VOP* instructions like ADDC use VReg32 as the register class + // for source 0, because they read VCC and can't take an SGPR as an + // argument due to constant bus restrictions. + if (OpNo == 1 && (Desc.TSFlags & (SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | + SIInstrFlags::VOPC))) + return true; unsigned RegClass = Desc.OpInfo[OpNo].RegClass; return (AMDGPU::SSrc_32RegClassID == RegClass) || |
