1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
index d54412c465e..930aed1c38f 100644
--- a/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
@@ -91,7 +91,7 @@ public:
   };
 
   void addImmOperands(MCInst &Inst, unsigned N) const {
-    Inst.addOperand(MCOperand::CreateImm(getImm()));
+    Inst.addOperand(MCOperand::createImm(getImm()));
   }
 
   StringRef getToken() const {
@@ -99,7 +99,7 @@ public:
   }
 
   void addRegOperands(MCInst &Inst, unsigned N) const {
-    Inst.addOperand(MCOperand::CreateReg(getReg()));
+    Inst.addOperand(MCOperand::createReg(getReg()));
   }
 
   void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
@@ -110,7 +110,7 @@ public:
   }
 
   void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
-    Inst.addOperand(MCOperand::CreateImm(
+    Inst.addOperand(MCOperand::createImm(
         Reg.Modifiers == -1 ? 0 : Reg.Modifiers));
     addRegOperands(Inst, N);
   }
@@ -120,7 +120,7 @@ public:
       addImmOperands(Inst, N);
     else {
       assert(isExpr());
-      Inst.addOperand(MCOperand::CreateExpr(Expr));
+      Inst.addOperand(MCOperand::createExpr(Expr));
     }
   }
 
@@ -948,7 +948,7 @@ void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
   ((AMDGPUOperand &)*Operands[Offset0Idx]).addImmOperands(Inst, 1); // offset0
   ((AMDGPUOperand &)*Operands[Offset1Idx]).addImmOperands(Inst, 1); // offset1
   ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
-  Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
+  Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
 }
 
 void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
@@ -981,7 +981,7 @@ void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
     unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
     ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
   }
-  Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
+  Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
 }