diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 4 |
4 files changed, 13 insertions, 13 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 4f88d35deaf..1e323849d1e 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -215,7 +215,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { const TargetInstrInfo &TII = *TM.getInstrInfo(); MachineBasicBlock &EntryBB = *Fn.begin(); - DebugLoc dl = DebugLoc::getUnknownLoc(); + DebugLoc dl; // Emit the following code into the entry block: // InVRSAVE = MFVRSAVE // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE @@ -253,7 +253,7 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = MF->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); - DebugLoc dl = DebugLoc::getUnknownLoc(); + DebugLoc dl; if (PPCLowering.getPointerTy() == MVT::i32) { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 337b0d74c33..dda530eef43 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1122,7 +1122,7 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, // With PIC, the first instruction is actually "GR+hi(&G)". Hi = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, - DebugLoc::getUnknownLoc(), PtrVT), Hi); + DebugLoc(), PtrVT), Hi); } Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); @@ -1155,7 +1155,7 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { // With PIC, the first instruction is actually "GR+hi(&G)". Hi = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, - DebugLoc::getUnknownLoc(), PtrVT), Hi); + DebugLoc(), PtrVT), Hi); } Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); @@ -1192,7 +1192,7 @@ SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { // With PIC, the first instruction is actually "GR+hi(&G)". Hi = DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, - DebugLoc::getUnknownLoc(), PtrVT), Hi); + DebugLoc(), PtrVT), Hi); } return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); @@ -1233,7 +1233,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, // With PIC, the first instruction is actually "GR+hi(&G)". Hi = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, - DebugLoc::getUnknownLoc(), PtrVT), Hi); + DebugLoc(), PtrVT), Hi); } Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 82c637efaf2..6b0a282af09 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -199,7 +199,7 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - DebugLoc DL = DebugLoc::getUnknownLoc(); + DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); BuildMI(MBB, MI, DL, get(PPC::NOP)); @@ -317,7 +317,7 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond) const { // FIXME this should probably have a DebugLoc argument - DebugLoc dl = DebugLoc::getUnknownLoc(); + DebugLoc dl; // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -350,7 +350,7 @@ bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, return false; } - DebugLoc DL = DebugLoc::getUnknownLoc(); + DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); if (DestRC == PPC::GPRCRegisterClass) { @@ -380,7 +380,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const{ - DebugLoc DL = DebugLoc::getUnknownLoc(); + DebugLoc DL; if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) @@ -635,7 +635,7 @@ PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, const TargetRegisterClass *RC) const { MachineFunction &MF = *MBB.getParent(); SmallVector<MachineInstr*, 4> NewMIs; - DebugLoc DL = DebugLoc::getUnknownLoc(); + DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 44c5fe672f8..9363aa8b756 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1281,7 +1281,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - DebugLoc dl = DebugLoc::getUnknownLoc(); + DebugLoc dl; bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || !MF.getFunction()->doesNotThrow() || UnwindTablesMandatory; @@ -1521,7 +1521,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); unsigned RetOpcode = MBBI->getOpcode(); - DebugLoc dl = DebugLoc::getUnknownLoc(); + DebugLoc dl; assert( (RetOpcode == PPC::BLR || RetOpcode == PPC::TCRETURNri || |
