7 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCSchedule440.td b/llvm/lib/Target/PowerPC/PPCSchedule440.td
index 04a43bc0325..e4a2c3b474d 100644
--- a/llvm/lib/Target/PowerPC/PPCSchedule440.td
+++ b/llvm/lib/Target/PowerPC/PPCSchedule440.td
@@ -602,6 +602,8 @@ def PPC440Model : SchedMachineModel {
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
 
+  let CompleteModel = 0;
+
   let Itineraries = PPC440Itineraries;
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
index 21a357a2efc..9cdfd0b996d 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
@@ -166,6 +166,8 @@ def PPCA2Model : SchedMachineModel {
                        // Itineraries are queried instead.
   let MispredictPenalty = 13;
 
+  let CompleteModel = 0;
+
   let Itineraries = PPCA2Itineraries;
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
index 36b8517dabf..262c7150800 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
@@ -316,5 +316,7 @@ def PPCE500mcModel : SchedMachineModel {
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
 
+  let CompleteModel = 0;
+
   let Itineraries = PPCE500mcItineraries;
 }
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
index 7c2693ef0d4..642a5ae726e 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
@@ -376,5 +376,7 @@ def PPCE5500Model : SchedMachineModel {
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
 
+  let CompleteModel = 0;
+
   let Itineraries = PPCE5500Itineraries;
 }
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG5.td b/llvm/lib/Target/PowerPC/PPCScheduleG5.td
index a3b73ab4454..a001b592312 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleG5.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleG5.td
@@ -124,6 +124,8 @@ def G5Model : SchedMachineModel {
                        // Itineraries are queried instead.
   let MispredictPenalty = 16;
 
+  let CompleteModel = 0;
+
   let Itineraries = G5Itineraries;
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
index 267f5672618..26c80c92c90 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
@@ -391,6 +391,8 @@ def P7Model : SchedMachineModel {
   // Try to make sure we have at least 10 dispatch groups in a loop.
   let LoopMicroOpBufferSize = 40;
 
+  let CompleteModel = 0;
+
   let Itineraries = P7Itineraries;
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP8.td b/llvm/lib/Target/PowerPC/PPCScheduleP8.td
index 69e6d05c660..b7083e6bafe 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP8.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP8.td
@@ -400,6 +400,8 @@ def P8Model : SchedMachineModel {
   // Try to make sure we have at least 10 dispatch groups in a loop.
   let LoopMicroOpBufferSize = 60;
 
+  let CompleteModel = 0;
+
   let Itineraries = P8Itineraries;
 }