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-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetMachine.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 2babc8f6453..c934668a80c 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -88,6 +88,10 @@ EnableMachineCombinerPass("ppc-machine-combiner",
cl::desc("Enable the machine combiner pass"),
cl::init(true), cl::Hidden);
+static cl::opt<bool>
+ ReduceCRLogical("ppc-reduce-cr-logicals",
+ cl::desc("Expand eligible cr-logical binary ops to branches"),
+ cl::init(false), cl::Hidden);
extern "C" void LLVMInitializePowerPCTarget() {
// Register the targets
RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
@@ -392,6 +396,9 @@ void PPCPassConfig::addMachineSSAOptimization() {
if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
!DisableVSXSwapRemoval)
addPass(createPPCVSXSwapRemovalPass());
+ // Reduce the number of cr-logical ops.
+ if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
+ addPass(createPPCReduceCRLogicalsPass());
// Target-specific peephole cleanups performed after instruction
// selection.
if (!DisableMIPeephole) {
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