diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCSchedule440.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCSchedule440.td | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCSchedule440.td b/llvm/lib/Target/PowerPC/PPCSchedule440.td index 780fa4779b4..218fed248a3 100644 --- a/llvm/lib/Target/PowerPC/PPCSchedule440.td +++ b/llvm/lib/Target/PowerPC/PPCSchedule440.td @@ -258,6 +258,13 @@ def PPC440Itineraries : ProcessorItineraries< InstrStage<2, [P440_LWB]>], [5, 2, 1, 1], [P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], + [5, 2, 1, 1], + [P440_GPR_Bypass, P440_GPR_Bypass]>, InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>, InstrStage<1, [P440_LRACC]>, InstrStage<1, [P440_AGEN]>, @@ -307,6 +314,13 @@ def PPC440Itineraries : ProcessorItineraries< InstrStage<1, [P440_LWB]>], [5, 2, 1, 1], [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], + [5, 2, 1, 1], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>, InstrStage<1, [P440_LRACC]>, InstrStage<1, [P440_AGEN]>, @@ -321,6 +335,13 @@ def PPC440Itineraries : ProcessorItineraries< InstrStage<1, [P440_LWB]>], [4, 1, 1], [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], + [4, 1, 1], + [NoBypass, P440_GPR_Bypass]>, InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>, InstrStage<1, [P440_LRACC]>, InstrStage<1, [P440_AGEN]>, @@ -351,6 +372,13 @@ def PPC440Itineraries : ProcessorItineraries< InstrStage<2, [P440_LWB]>], [2, 1, 1, 1], [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], + [2, 1, 1, 1], + [NoBypass, P440_GPR_Bypass]>, InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>, InstrStage<1, [P440_IRACC], 0>, InstrStage<4, [P440_LWARX_Hold], 0>, |
